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RT7204E Datasheet(PDF) 35 Page - Richtek Technology Corporation |
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RT7204E Datasheet(HTML) 35 Page - Richtek Technology Corporation |
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35 / 45 page ![]() F RT7204E Copyright © 2024 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. RT7204E_DS-00 May 2024 www.richtek.com 35 VDD t USBP t 5V VVDD_ON VBUS t IOUT t Power-saving mode threshold Debounce time to enter power-saving mode Power-Saving Mode t Blocking MOS VGS threshold tUSBP_SS Figure 8. The Output Sequence during Start-Up 16.4 Output Voltage Rises and Falls When the protocol is detected, the reference voltage VREF_CV can be set by the request of UFP. Both the rise time and fall time of output voltages should be less than the defined specification, as shown in Figure 9. VVDD t VREF_CV 5V 20V 0.5V 2.0V Slope (2V – 0.5V) / trise < trise t (a) Output Voltage Rising VVDD 5V 20V 0.5V 2.0V Slope (0.5V – 2V) / tfall IDD_DIS tDIS_VDD (Programmable) VREF_CV < tfall t t t (b) Output Voltage Falling Figure 9. Output Voltage Transient Waveforms |
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