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ISM330BX Datasheet(PDF) 119 Page - STMicroelectronics |
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ISM330BX Datasheet(HTML) 119 Page - STMicroelectronics |
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119 / 150 page ![]() 11.30 SFLP_ODR (5Eh) Sensor fusion low-power output data rate configuration register (R/W) Table 247. SFLP_ODR register 0(1) 1(2) SFLP_GAME _ODR_2 SFLP_GAME _ODR_1 SFLP_GAME _ODR_0 0(1) 1(2) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 248. SFLP_ODR register description SFLP_GAME_ODR_[2:0] ODR configuration of the SFLP game algorithm: (000: 15 Hz; 001: 30 Hz; 010: 60 Hz; 011: 120 Hz (default); 100: 240 Hz; 101: 480 Hz) 11.31 FSM_ODR (5Fh) Finite state machine output data rate configuration register (R/W) Table 249. FSM_ODR register 0(1) 1(2) FSM_ODR_2 FSM_ODR_1 FSM_ODR_0 0(1) 1(2) 1(2) 1. This bit must be set to 0 for the correct operation of the device. 2. This bit must be set to 1 for the correct operation of the device. Table 250. FSM_ODR register description FSM_ODR_[2:0] Finite state machine ODR configuration: (000: 15 Hz; 001: 30 Hz (default); 010: 60 Hz; 011: 120 Hz; 100: 240 Hz; 101: 480 Hz; 110: 960 Hz) ISM330BX Embedded functions register description DS14588 - Rev 2 page 119/150 |
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