Preliminary PI3033B datasheet

Page 11 of 13 Date: 03/18/05

(2)

Prohibit crossing time is to insure that no two start pulses are locked into the shift

register for any single scan time. Since the start pulse is entered into the shift

register during its active high level when the CP clock edges falls, the active high

of the start pulse is permitted only during one falling, CP, clock edges for any

given scan. Otherwise, multiple start pulses will load into the shift register.

(3)

Pixel delay times and settling time depend on the output amplifier, which is

employed. These values, tdl and ts/h, are measured with the amplifier see in

Figure 9. Typical A6 CIS Module Circuit using the PI3033B sensors. Note, the

impulse signal current out of the device has pulse width ~ 30 ns. Hence, the

faster the amplifier with a faster settling time will yield a signal video pulse with

faster rise and settle times.

Typical A6 CIS Module Circuit

See Figure 9. Typical A6 CIS Module Circuit using the PI3033B sensors. The circuit is provided as

reference to illustrate the interconnection of the PI3033B for a serially cascaded line of image sensors.

It is a typical A6 size CIS module produced by PIC. It provides the first time user with additional insight

for designing a CIS module and supplements the circuit descriptions given in the section, Signal

Output Conversion, page 5.

The difference is in the arrangement of the two shunt switches, U2D, and U2A. U2D is a counterpart

to SW in

Figure 5. Video Output Test and Application Circuit. A DC restoration capacitor, C20,

with value of 100pf added between the shunts switch. The first, U2D, clamps the video line to

ground to reset the image sensors. Simultaneously the second, U2A, clamps the node

between C20 and amplifier input to a output reference bias voltage that is on the node

between R4 and R9. These resistors are voltage divider that sets the DC operating level of

the amplifier’s output by applying same bias voltage to both inputs of the amplifier

(See next page for the Typical A6 CIS Module Circuit.)