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AD7293BCPZ Datasheet(PDF) 44 Page - Analog Devices |
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AD7293BCPZ Datasheet(HTML) 44 Page - Analog Devices |
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44 / 79 page ![]() AD7293 Data Sheet Rev. D | Page 44 of 79 Bit Number(s) Bit Name Description D3 Closed-Loop 3 0: closed loop is disabled (default) 1: closed loop is enabled D2 Closed-Loop 2 0: closed loop is disabled (default) 1: closed loop is enabled D1 Closed-Loop 1 0: closed loop is disabled (default) 1: closed loop is enabled D0 Closed-Loop 0 0: closed loop is disabled (default) 1: closed loop is enabled Table 48. PA_ON Control Register (Register 0x29) Bit Number(s) Bit Name Description [D15:D10] Reserved Reserved D9 PA_ON enable 0: PA_ON signal is in the off state (default) 1: PA_ON signal is in the on state D8 PA_ON trigger 0: no control 1: AVSS/AVDD alarm or ALERT0 triggers PA_ON (default) [D7:D6] Reserved Reserved D5 SLEEP1 snooze 0: no control 1: PA_ON snooze after SLEEP1 enable (default) D4 SLEEP0 snooze 0: no control 1: PA_ON snooze after SLEEP0 enable (default) [D3:D2] Reserved Reserved D1 PA_ON SLEEP1 0: no control (default) 1: PA_ON controlled by the SLEEP1 pin D0 PA_ON SLEEP0 0: no control (default) 1: PA_ON controlled by the SLEEP0 pin Table 49. Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Bit Number(s) Bit Name Description [D15:D7] Reserved Reserved [D6:D0] B6 to B0 Ramp time bits configure the ramp time for the DACs in closed-loop mode 0000000 = no ramp function (default) 0000001 to 0010000 = 4 ms 0010001 = 4.25 ms … 1111110 = 31.5 ms 1111111 = 31.75 ms Table 50. Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Bit Number(s) Bit Name Description D15 CL3_FR 0: Closed-Loop 3 fast ramp disable 1: Closed-Loop 3 fast ramp enable (default) [D14:D12] CL3_CAP_TRIM[2:0] 000: not applicable 001: 2.352 ms 010: 1.218 ms 011: 840 µs (default) 100: 650 µs 101: 538 µs 110: 462 µs 111: 408 µs |
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