AD7293BCPZ datasheet(27/79 Pages) AD

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Data Sheet

AD7293

Rev. D | Page 27 of 79

The bipolar DACs power-on reset and clamp value is dependent

on the VCLAMP0 and VCLAMP1 voltage level. After a power-on reset

or when the digital SLEEP0 or SLEEP1 pin is configured to trigger

a clamp, the bipolar DAC outputs reset to the clamp value (see

Table 18).

After a power-on reset or when the digital SLEEP0 or SLEEP1

pin is configured to trigger clamping, the unipolar DAC outputs

default to 0 V.

Software Clamping: Internal ALERT0 Routing

There is an option to allow the ALERT0 alert to trigger the

clamp function. The DACs power back up when the alert is

cleared without an additional write to the DAC enable registers.

Bit D1 of the general register in the configuration page allows

ALERT0 control over the clamping function of the four bipolar

DACs.

PMOS Drain Switch Control

The AD7293 PA_ON output pin is capable of driving an

external PMOS switch. This external PMOS turns on or off the

drain current to a PA field effect transistor (FET). The PA_ON

output pin controls the device during power-up and power-down.

This feature can also be used as a protection feature when an

alert condition is detected because ALERT0 alerts or an AVSS or

AVDD supply failure can be used to trigger the PA_ON pin.

PAVDD determines the maximum voltage at the output of the

PA_ON pin. The off state is equal to PAVDD while the on state is

equal to AGND. The default state of the PA_ON signal is off.

PAVDD

PA_ON

PMOS

CONTROL

RSENSE

V p-p

PMOS

DRAIN

SWITCH

RSx+

RSx–

CURRENT

SENSOR

PA FET

FILTER

RF IN

RF OUT

Figure 45. PMOS Drain Switch Control

REFERENCE

The AD7293 has one high performance, 2.5 V on-chip reference

accessed via the VREFOUT pin. Noise performance can be improved

by the addition of a 10 nF capacitor between the VREFOUT pin and

the AGND pin. Connect VREFOUT to the VREFIN pin to use the

on-chip reference of the AD7293. An internal amplifier attenu-

ates to the ADC core, making the voltage at the ADC, REFADC =

1.25 V, half of VREFIN = 2.5 V. Use the REFADC pin for measurement

purposes only.

A 220 nF capacitor is required on the REFADC pin and must be

placed as close to the AD7293 as possible with no vias. The

internal reference typically requires 20 ms to power up and settle

when using a 220 nF decoupling capacitor on the REFADC pin.

Buffer the internal reference before it is used by external circuitry.

The AD7293 can also operate with an external reference of

2.5 V connected to the VREFIN pin.

If using an external reference, select a low temperature coefficient

specification, such as the ADR4525, to reduce the temperature

dependence of the system output voltage on ambient conditions.

VDRIVE FEATURE

The AD7293 also has a VDRIVE feature that controls the voltage at

which the SPI operates. Connect the VDRIVE pin to the supply to

which the SPI bus is pulled. The VDRIVE pin sets the input and

output threshold levels for the digital logic pins. The VDRIVE

feature allows the AD7293 to interface with 1.8 V, 3.3 V, and 5 V

processors.

OPEN-LOOP MODE

In open-loop mode, the default mode of operation, the current

sense amplifiers and bipolar DACs operate independently.

CLOSED-LOOP MODE

Alternatively, the AD7293 current sensors and bipolar DACs

can operate as four independent closed-loop drain current

controllers (closed-loop mode).

In closed-loop operation, the drain current through the PA FET

is set and automatically maintained by the PA controller through a

regulation circuit that includes the DAC and current sense moni-

tor. The control loop sets the PA bias current and continuously

maintains a constant voltage across the sense resistor (VSENSE =

ISENSE × RSENSE). When the DAC current updates, the closed-loop

adjusts the gate voltage of the PA until the drain current matches

the corresponding DAC code. The continuous regulation of the

loop compensates for variations of the PA threshold or voltage

drop on the LPF due to the PA gate current. The integrator

leads to a smooth transition on the output of the pin.

RSx+

RSx–

LPF

BIPOLAR

DAC

(PROGRAMMABLE

RAMP TIME)

AD7293

Figure 46. Closed-Loop Control

AD7293BCPZ Datasheet(PDF) 27 Page - Analog Devices

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