M65KA512AB datasheet(20/55 Pages) STMICROELECTRONICS

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M65KA512AB

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5.1

Mode Register description

The Mode Register is used to select the CAS Latency (2 or 3), the Burst Type (sequential,

interleaved), the Burst Length (1-, 2-, 4-, 8-word width or full page).

It is loaded by issuing a Mode Register Set command that programs A0 to A12 address bits.

The values placed on the address lines are then latched into the Mode Register. BA0-BA1

must be set to ‘0’.

See Table 4: Mode Register Definition, for more details.

5.2

Burst Length bits (MR0 to MR2)

Bits 0 to 2 (MR0 to MR2) of the Mode Register are used to configure the Burst Length. The

burst Length is the number of words that are output or input during a read or a write

operation, respectively. It can be set to 1, 2, 4, 8 words or full page.

5.3

Burst Type bit (MR3)

Bit 3 (MR3) of the Mode Register is used to set the Burst Type. The Burst Type defines the

order in which the address locations are accessed during a burst operation. It can be either

sequential or interleaved.

The type of application microprocessor must be taken into account when selecting the Burst

Type: some microprocessor cache systems are optimized for sequential addressing and

others for interleaved addressing.

Both Burst Types support burst length of 1, 2, 4 or 8 words. Full page burst is also available

when the sequential burst type is selected.

5.4

CAS Latency bits (MR4 to MR6)

The CAS latency is the most critical of the Mode Register parameters. It defines the number

of clocks cycles between the detection of a Read command to the first data output valid. It

can be set to two or three clock cycles.

The value of this parameter is determined by the frequency of the clock and the speed grade

of the device.

Table 4.

Mode Register Definition

Address

Bits

Mode

description

Value

Description

A12-A7

0000000

A6-A4

MR6-MR4

CAS Latency bits

010

2 clock cycles

011

3 clock cycles(1)

Other configurations reserved

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