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TLV9062IDDFR Datasheet(PDF) 39 Page - Texas Instruments |
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TLV9062IDDFR Datasheet(HTML) 39 Page - Texas Instruments |
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39 / 86 page  www.ti.com PACKAGE OUTLINE C 0.22 0.08 TYP 0.15 2.4 1.8 2X 0.65 1.3 1.1 MAX 0.1 0.0 TYP 5X 0.33 0.15 NOTE 5 0.1 C A B 0.46 0.26 TYP 8 0 TYP 1.3 A 2.15 1.85 B 1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max height DCK0005A SMALL OUTLINE TRANSISTOR 4214834/E 06/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C A B 1 3 4 5 2 INDEX AREA PIN 1 NOTE 4 NOTE 5 GAGE PLANE SEATING PLANE 0.1 C SCALE 5.600 ALTERNATIVE PACKAGE SINGULATION VIEW |
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