TDA8433 datasheet(2/25 Pages) PHILIPS

2 / 25 page

August 1991

Philips Semiconductors

Product speciﬁcation

Deﬂection processor for computer

controlled TV receivers

TDA8433

FEATURES

• I2C-bus interface

• Input for vertical sync

• Sawtooth generator with amplitude

independent of frequency

• Vertical deflection output stage

driver

• East-west raster correction drive

output

• EHT modulation input

• Changes picture width and height

without affecting geometry.

GENERAL DESCRIPTION

The TDA8433 is an I2C-bus

controlled deflection processor which,

together with a sync processor (e.g.

TDA2579A, see Fig.6), contains the

control and drive functions of the

deflection part in a computer

controlled TV receiver. The TDA8433

replaces all picture geometry settings

which were previously set manually

during manufacture.

QUICK REFERENCE DATA

Note to quick reference data

1. VRin = 0; V-S-corr = 0; Vshift = 20 H; Vampl = 20 H.

ORDERING INFORMATION

Note

1. SOT101-1; 1996 December 2.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

VCC

supply voltage (pin 12)

10.8

12.0

13.2

ICC

supply current (pin 12)

vertical sync trigger level

−

V21

vertical feedback (note 1)

DC level

−1.7

1.85

2.05

AC level

1.65

1.8

1.95

V24

EHT compensation operating range

1.7

−

V11-13

inputs for control register data:

not locked to video

−

0.7

at 50 Hz status

0.8 VCC

−−

at 60 Hz status

−−

0.7 VCC

V10-13

HCENT comparator switching level

−

V17

−

V14-13

SDA I2C-bus switching level data input

−

3.5

−

V15

SCL I2C-bus switching level clock input

−

3.5

−

device selection where:

Ao = '1'

9.0

−

VCC

Ao = '0'

−

2.0

EXTENDED TYPE NUMBER

PACKAGE

PINS

PIN POSITION

MATERIAL

CODE

TDA8433

DIL

plastic

SOT101(1)

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