TCN75 datasheet(6/20 Pages) MICROCHIP

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TCN75

DS21490C-page 6

3.0

DETAILED DESCRIPTION

A typical TCN75 hardware connection is shown in

Figure 3-1.

FIGURE 3-1:

Typical Application

3.1

Serial Data (SDA)

Bidirectional. Serial data is transferred in both

directions using this pin.

3.2

Serial Clock (SCL)

Input. Clocks data into and out of the TCN75.

3.3

INT/CMPTR

Open Collector, Programmable Polarity. In Comparator

mode,

unconditionally

driven

active

any

time

temperature exceeds the value programmed into the

TSET register. INT/CMPTR will become inactive when

temperature subsequently falls below the THYST set-

ting. (See Section 5.0 “Register Set and Program-

mer’s ModeL”, Register Set and Programmer’s

Model). In Interrupt mode, INT/CMPTR is also made

active by TEMP exceeding TSET; it is unconditionally

reset to its inactive state by reading any register via the

2-wire bus. If and when temperature falls below THYST,

INT/CMPTR is again driven active. Reading any regis-

ter will clear the THYST interrupt. In Interrupt mode, the

INT/CMPTR output is unconditionally reset upon enter-

ing Shutdown mode. If programmed as an active-low

output, it can be wire-ORed with any number of other

open collector devices. Most systems will require a

pull-up resistor for this configuration.

Note that current sourced from the pull-up resistor

causes power dissipation and may cause internal heat-

ing of the TCN75. To avoid affecting the accuracy of

ambient temperature readings, the pull-up resistor

should be made as large as possible. INT/CMPTR’s

output polarity may be programmed by writing to the

INT/CMPTR POLARITY bit in the CONFIG register.

The default is active low.

3.4

Address (A2, A1, A0)

Inputs. Sets the three Least Significant bits of the

TCN75 8-bit address. A match between the TCN75’s

address and the address specified in the serial bit

stream must be made to initiate communication with

the TCN75. Many protocol-compatible devices with

other addresses may share the same 2-wire bus.

3.5

Slave Address

The four Most Significant bits of the Address Byte (A6,

A5, A4, A3) are fixed to 1001[B]. The states of A2, A1

and A0 in the serial bit stream must match the states of

the A2, A1 and A0 address inputs for the TCN75 to

respond with an Acknowledge (indicating the TCN75 is

on the bus and ready to accept data). The Slave

Address is represented in Table 3-1.

SDA

SCL

+VDD (3V to 5.5V)

Address

(Set as Desired)

I2C™ Interface

CBypass

To Controller

0.1 µF Recommended

Unless Device is Mounted

Close to CPU

INT/CMPTR

TCN75

TABLE 3-1:

TCN75 SLAVE ADDRESS

MSB

LSBS

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