MCP6G01-ESLASHMS datasheet(20/38 Pages) MICROCHIP

20 / 38 page

MCP6G01/1R/1U/2/3/4

DS22004B-page 20

4.1.4

INPUT VOLTAGE AND CURRENT

LIMITS

The ESD protection on the inputs can be depicted as

shown in Figure 4-2. This structure was chosen to

protect the input transistors, and to minimize input bias

current (IB). The input ESD diodes clamp the inputs

when they try to go more than one diode drop below

VSS. They also clamp any voltages that go too far

above VDD; their breakdown voltage is high enough to

allow normal operation, and low enough to bypass ESD

events within the specified limits.

FIGURE 4-2:

Simplified Analog Input ESD

Structures.

In order to prevent damage and/or improper operation

of these amplifiers, the circuits they are in must limit the

currents (and voltages) at the VIN pins (see Section

“Absolute Maximum Ratings †” at the beginning of

Section 1.0 “Electrical Characteristics”). Figure 4-3

shows the recommended approach to protecting these

inputs. The internal ESD diodes prevent the input pins

(VIN) from going too far below ground, and the resistor

R1 limits the possible current drawn out of the input pin.

Diode D1 prevents the input pin (VIN) from going too far

above VDD. When implemented as shown, resistor R1

also limits the current through D1.

FIGURE 4-3:

Protecting the Analog

Inputs.

It is also possible to connect the diode to the left of the

resistor R1. In this case, the current through the diode

D1 needs to be limited by some other mechanism. The

resistor then serves as in-rush current limiter; the DC

current into the input pin (VIN) should be very small.

A significant amount of current can flow out of the

inputs when the common mode voltage (VCM) is below

ground (VSS); see Figure 2-17. Applications that are

high impedance may need to limit the useable voltage

range.

4.1.5

RAIL-TO-RAIL OUTPUT

The maximum output voltage swing is the maximum

swing possible under a particular amplifier load current.

The amplifier load current is the sum of the external

load current (IOUT) and the current through the ladder

resistance (ILAD); see Figure 4-4.

EQUATION 4-2:

FIGURE 4-4:

Amplifier Load Current.

See Figure 2-20 for the typical output headroom

(VDD – VOH or VOL – VSS) as a function of amplifier

load current.The specification table states the output

can reach within 10 mV of either supply rail when

RL = 100 kΩ.

4.2

Resistor Ladder

The

resistor

ladder

shown

Figure 4-1

(RLAD =RF +RG) sets the gain. Placing the gain

switches in series with the inverting input reduces the

parasitic capacitance, distortion, and gain mismatch.

RLAD is an additional load on the output of the SGA and

causes additional current draw from the supplies.

When CS is high, the SGA is shut down (low power).

RLAD is still attached to the VOUT and VSS pins. Thus,

these pins and the internal amplifier’s inverting input

are all connected through RLAD and the output is not

high-Z (unlike the internal op amp).

RLAD contributes to the output noise; see Figure 2-9.

Bond

Pad

Bond

Pad

Bond

Pad

VDD

VIN

VSS

to the rest of

Input

Stage

the amplifier

MCP6G0X

VDD

R1 ≥

VSS – (minimum expected V1)

2mA

VOUT

VIN

Where:

Amplifier Load Current

IOUT ILAD

ILAD

VOUT VSS

–

()

RLAD

---------------------------------

VOUT

VSS

RLAD

IOUT

ILAD

MCP6G0X

VIN

MCP6G01-E/MS Datasheet(PDF) 20 Page - Microchip Technology

MCP6G01-E/MS Datasheet(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL