TDA8765HSLASH5 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1999 Jan 06

Philips Semiconductors

Preliminary speciﬁcation

10-bit high-speed Analog-to-Digital

Converter (ADC)

TDA8765

Voltage controlled regulator input Vref (referenced to AGND); note 2

Vref

full-scale ﬁxed voltage

VCCA =5V

−

3.175

−

VI(p-p) − VI(p-p) input voltage amplitude

(peak-to-peak value)

Vref =VCCA − 1.825 V

−

2.0

−

Iref

input current at Vref

−

0.5

µA

Outputs (referenced to OGND)

DIGITAL OUTPUTS D11 TO D0 AND IR (REFERENCED TO OGND)

VOL

LOW-level output voltage

IOL =2mA

−

0.5

VOH

HIGH-level output voltage

IOH = −0.4 mA

VCCO − 0.5

−

VCCO

output current in 3-state

output level between 0.5 V

and VCCO

−20

−

+20

µA

Switching characteristics

CLOCK FREQUENCY fCLK; see Fig.5

fCLK(min)

minimum clock frequency

SH = HIGH

−−

MHz

SH = LOW

−−

kHz

fCLK(max)

maximum clock frequency

TDA8765H/4

−−

MHz

TDA8765H/5

−−

MHz

tCLKH

clock pulse width HIGH

8.5

−−

tCLKL

clock pulse width LOW

8.5

−−

Analog signal processing; 50% clock duty factor; VI − VI = 2.0 V; Vref =VCCA− 1.825 V; see Table 1

LINEARITY

INL

integral non-linearity

fCLK = 4 MHz; fi = 400 kHz

−±0.5

±1.75

LSB

DNL

differential non-linearity

fCLK = 4 MHz; fi = 400 kHz;

no missing code

−±0.3

±0.5

LSB

Eoffset

offset error

VCCA =VCCD =VCCO =5V;

Tamb =25 °C; VI = VI;

output code = 511

tbf

−11

tbf

gain error amplitude; spread

from device to device

VCCA =VCCD =VCCO =5V;

Tamb =25 °C;

VI(p-p) − VI(p-p) = 2.0 V

−5

−

%FS

BANDWIDTH (fCLK = 55 MHz); note 3

analog bandwidth

−3 dB; full-scale input

tbf

200

−

MHz

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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