93LC66B-ESLASHMS datasheet(7/28 Pages) MICROCHIP

7 / 28 page

DS21795C-page 7

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C

2.4

Erase

The ERASE instruction forces all data bits of the speci-

fied address to the logical ‘1’ state. CS is brought low

following the loading of the last address bit. This falling

edge of the CS pin initiates the self-timed program-

ming cycle, except on ‘93C’ devices where the rising

edge of CLK before the last address bit initiates the

write cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

Note:

Issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

FIGURE 2-1:

ERASE TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-2:

ERASE TIMING FOR 93C DEVICES

CLK

TCSL

Check Status

AN-1

AN-2

•••

TSV

TCZ

Busy

Ready

High-Z

TWC

High-Z

CLK

TCSL

Check Status

AN-1

AN-2

•••

TSV

TCZ

Busy

Ready

High-Z

TWC

High-Z

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