93LC66B-ESLASHMS datasheet(11/28 Pages) MICROCHIP

11 / 28 page

DS21795C-page 11

93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C

2.9

Write All (WRAL)

The Write All (WRAL) instruction will write the entire

memory array with the data specified in the command.

For 93AA66A/B/C and 93LC66A/B/C devices, after the

last data bit is clocked into DI, the falling edge of CS

initiates the self-timed auto-erase and programming

cycle. For 93C66A/B/C devices, the self-timed auto-

erase and programming cycle is initiated by the rising

edge of CLK on the last data bit. Clocking of the CLK

pin is not necessary after the device has entered the

WRAL cycle. The WRAL command does include an

automatic ERAL cycle for the device. Therefore, the

WRAL

instruction does not require an ERAL instruction,

but the chip must be in the EWEN status.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL).

Note:

Issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

VCC must be

≥ 4.5V for proper operation of WRAL.

FIGURE 2-10:

WRAL TIMING FOR 93AA AND 93LC DEVICES

FIGURE 2-11:

WRAL TIMING FOR 93C DEVICES

CLK

High-Z

•••

High-Z

Busy

Ready

TWL

VCC must be

≥ 4.5V for proper operation of WRAL.

TCSL

TSV

TCZ

CLK

High-Z

•••

High-Z

Busy

Ready

TWL

TCSL

TSV

TCZ

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