TDA9321 datasheet(12/44 Pages) PHILIPS

12 / 44 page

1998 Dec 16

Philips Semiconductors

Preliminary speciﬁcation

I2C-bus controlled TV input processor

TDA9321H

Table 5

Motion Adaptive Colour Plus (MACP)

Note

1. The black set-up will only be present in a norm sync

condition.

Table 6

Helper output blanking (PALplus/EDTV-2)

Note

1. X = don’t care.

Table 7

PALplus helper demodulation active

Note

1. Black and helper set-up will only be present in a norm

sync condition.

Table 8

Forced colour on

Table 9

Automatic colour limiting

MACP

MODE

internal 4.43 MHz trap used

external MACP chrominance ﬁltering used;

4.43 MHz trap bypassed and black set-up

200 mV; note 1

HOB

HBC

SNR

BLANKING

0X(1)

X(1)

off

X(1)

110

off

111

CONDITIONS

0off

on; PALplus mode with helper set-up 400 mV

and black set-up 200 mV; note 1

FCO

MODE

not active

active

ACL

COLOUR LIMITING

not active

active

Table 10 Chrominance band-pass centre frequency

Table 11 Bypass of chrominance baseband delay line

Table 12 Gain luminance channel

Table 13 Y-delay adjustment; note 1

Note

1. For an equal delay of the luminance and chrominance

signal the delay must be set at a value of 280 ns

(YD3 to YD0 = 1011). This is only valid for a CVBS

signal without group delay distortions.

Table 14 Forced ﬁeld frequency

Note

1. When switched to this mode the divider will directly

switch to forced 60 Hz only.

CENTRE FREQUENCY

0fc

1.1

× fc

BPS

DELAY LINE MODE

active

bypassed

GAI1

GAI0

GAIN SETTING

−1dB

0 dB

+1 dB

+2 dB

YD0 to YD3

Y-DELAY

YD3

× 160 ns +

YD2

× 160 ns +

YD1

× 80 ns +

YD0

× 40 ns

FORF

FORS

FIELD FREQUENCY

auto (60 Hz when line not

synchronized)

forced 60 Hz; note 1

keep last detected ﬁeld frequency

auto (50 Hz when line not

synchronized)

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