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PIC18F4321 Datasheet(PDF) 14 Page - Microchip Technology |
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PIC18F4321 Datasheet(HTML) 14 Page - Microchip Technology |
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14 / 396 page ![]() PIC18F4321 FAMILY DS39689E-page 12 Preliminary © 2007 Microchip Technology Inc. TABLE 1-2: PIC18F2221/2321 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description SPDIP, SOIC, SSOP QFN MCLR/VPP/RE3 MCLR VPP RE3 126 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 96 I I I/O Analog Analog TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 10 7 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC, EC and INTIO modes, OSC2 pin outputs CLKO which has one-fourth the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input P = Power I2C = ST with I2C™ or SMB levels O = Output Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. |
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