PIC16F16-ESLASHPQTP datasheet(19/136 Pages) MICROCHIP

19 / 136 page

DS41206B-page 17

PIC16F716

2.3

PCL and PCLATH

The Program Counter (PC) is 13 bits wide. The low byte

comes from the PCL register, which is a readable and

writable register. The high byte (PC<12:8>) is not directly

readable or writable and comes from PCLATH. On any

Reset, the PC is cleared. Figure 2-3 shows the two

situations for the loading of the PC. The upper example

in Figure 2-3 shows how the PC is loaded on a write to

PCL (PCLATH<4:0>

→ PCH). The lower example in

Figure 2-3 shows how the PC is loaded during a CALL or

GOTO

instruction (PCLATH<4:3>

→ PCH).

2.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the

destination simultaneously causes the Program

Counter PC<12:8> bits (PCH) to be replaced by the

contents of the PCLATH register. This allows the entire

contents of the program counter to be changed by

writing the desired upper 5 bits to the PCLATH register.

When the lower 8 bits are written to the PCL register, all

13 bits of the program counter will change to the values

contained in the PCLATH register and those being

written to the PCL register.

A computed GOTO is accomplished by adding an offset

to the program counter (ADDWF PCL). Care should be

exercised when jumping into a look-up table or

program branch table (computed GOTO) by modifying

the PCL register. Assuming that PCLATH is set to the

table start address, if the table length is greater than

255 instructions or if the lower 8 bits of the memory

address rolls over from 0xFF to 0x00 in the middle of

the table, then PCLATH must be incremented for each

address rollover that occurs between the table

beginning and the target location within the table.

For more information refer to Application Note AN556,

“Implementing a Table Read” (DS00556).

2.3.2

PROGRAM MEMORY PAGING

The CALL and GOTO instructions provide 11 bits of

address to allow branching within any 2K program

memory page. When doing a CALL or GOTO instruction,

the upper bit of the address is provided by

PCLATH<3>. When doing a CALL or GOTO instruction,

the user must ensure that the page select bit is

programmed so that the desired program memory

page is addressed. If a RETURN from a CALL instruction

(or interrupt) is executed, the entire 13-bit PC is pushed

onto the stack. Therefore, manipulation of the

PCLATH<3> bit is not required for the RETURN

instructions (which POPs the address from the stack).

FIGURE 2-3:

LOADING OF PC IN

DIFFERENT SITUATIONS

2.4

Stack

The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Mid-range devices have an 8-level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space, and the Stack Pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN,

RETLW

or a RETFIE instruction execution.

PCLATH is not modified when the stack is PUSHed or

POPed.

After the stack has been PUSHed 8 times, the ninth

push overwrites the value that was stored from the first

push. The tenth push overwrites the second push (and

so on).

Instruction with

PCL as

Destination

ALU

Opcode <10:0>

GOTO

, CALL

PCLATH<4:3>

PCLATH

PCLATH<4:0>

12 1110

8 7

PCH

PCL

PCH

PCL

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