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PIC16F16-I/P Datasheet(PDF) 78 Page - Microchip Technology

Part # PIC16F16-I/P
Description  -bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM
PDF  136 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16F16-I/P Datasheet(HTML) 78 Page - Microchip Technology

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PIC16F716
DS41206B-page 76
© 2007 Microchip Technology Inc.
FIGURE 9-15:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
9.14
Program Verification/Code
Protection
If the code protection bit has not been programmed, the
on-chip program memory can be read out for
verification purposes.
9.15
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution, but are
readable and writable during program/verify. It is
recommended that only the 4 Least Significant bits of
the ID location are used.
9.16
In-Circuit Serial Programming™
PIC16F716
microcontrollers
can
be
serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
For complete details on serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Specification, (DS40245).
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4)
INT pin
INTF flag
(INTCON Reg.)
GIE bit
(INTCON Reg.)
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
PC
PC+1
PC+2
Inst(PC) = Sleep
Inst(PC - 1)
Inst(PC + 1)
Sleep
Processor in
Sleep
Interrupt Latency
(Note 3)
Inst(PC + 2)
Inst(PC + 1)
Inst(0004h)
Inst(0005h)
Inst(0004h)
Dummy cycle
PC + 2
0004h
0005h
Dummy cycle
TOST(2)
PC+2
Note
1:
XT, HS or LP Oscillator mode assumed.
2:
TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC Osc mode.
3:
GIE = 1 assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
4:
CLKOUT is not available in these osc modes, but shown here for timing reference.



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