PIC24HJ12GP201ESLASHML datasheet(34/234 Pages) MICROCHIP

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PIC24HJ12GP201/202

DS70282B-page 32

Preliminary

TABLE 3-22:

FUNDAMENTAL ADDRESSING MODES SUPPORTED

3.3.3

MOVE (MOV) INSTRUCTION

Move instructions provide a greater degree of

addressing flexibility than other instructions. In addition

to the addressing modes supported by most MCU

instructions, MOV instructions also support Register

Indirect with Register Offset Addressing mode, also

referred to as Register Indexed mode.

In summary, the following addressing modes are

supported by move instructions:

• Register Direct

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-bit Literal

• 16-bit Literal

3.3.4

OTHER INSTRUCTIONS

Besides the addressing modes outlined previously,

some instructions use literal constants of various sizes.

For example, BRA (branch) instructions use 16-bit

signed literals to specify the branch destination directly,

whereas the DISI instruction uses a 14-bit unsigned

literal field. In some instructions, such as ADD Acc, the

source of an operand or result is implied by the opcode

itself. Certain operations, such as NOP, do not have any

operands.

Addressing Mode

Description

File Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn forms the Effective Address (EA.)

The contents of Wn forms the EA. Wn is post-modified (incremented or

decremented) by a constant value.

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

(Register Indexed)

The sum of Wn and Wb forms the EA.

The sum of Wn and a literal forms the EA.

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA.

However, the 4-bit Wb (Register Offset)

field is shared by both source and

destination (but typically only used by

one).

Note:

Not all instructions support all the address-

ing modes given above. Individual instruc-

tions may support different subsets of

these addressing modes.

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