PIC24HJ12GP201ESLASHML datasheet(16/234 Pages) MICROCHIP

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PIC24HJ12GP201/202

DS70282B-page 14

Preliminary

2.3

CPU Control Registers

SR: CPU STATUS REGISTER

U-0

R/W-0

—

—DC

bit 15

bit 8

R/W-0(1)

R/W-0(2)

R-0

R/W-0

IPL<2:0>(2)

bit 7

bit 0

Legend:

C = Clear only bit

R = Readable bit

U = Unimplemented bit, read as ‘0’

S = Set only bit

W = Writable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented: Read as ‘0’

bit 8

DC: MCU ALU Half Carry/Borrow bit

1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits(2)

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled

110 = CPU Interrupt Priority Level is 6 (14)

101 = CPU Interrupt Priority Level is 5 (13)

100 = CPU Interrupt Priority Level is 4 (12)

011 = CPU Interrupt Priority Level is 3 (11)

010 = CPU Interrupt Priority Level is 2 (10)

001 = CPU Interrupt Priority Level is 1 (9)

000 = CPU Interrupt Priority Level is 0 (8)

bit 4

RA: REPEAT Loop Active bit

1 = REPEAT loop in progress

0 = REPEAT loop not in progress

bit 3

N: MCU ALU Negative bit

1 = Result was negative

0 = Result was non-negative (zero or positive)

bit 2

OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which

causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)

0 = No overflow occurred

bit 1

Z: MCU ALU Zero bit

1 = An operation which affects the Z bit has set it at some time in the past

0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)

bit 0

C: MCU ALU Carry/Borrow bit

1 = A carry-out from the Most Significant bit (MSb) of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

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