7.4

AC characteristics

Table 6. I²C operating conditions

Name

Description

Standard mode

Fast mode

Units

Min.

Max.

Min.

Max.

fSCL

SCL frequency of subdevice: processor

-

100

-

400

kHz

tHD;STA

Input low to clock low (start condition hold time)

4.0

-

0.6

-

µs

tLOW

Low period of SCL clock

4.7

-

1.3

-

µs

tHIGH

High period of SCL clock

4.0

-

0.6

-

µs

tSU;STA

Clock high to input transition/setup time for a (repeated) start

condition

4.7(1)

-

1.3(1)

-

µs

tHD;DAT

Clock low to input transition

0(2)

-(3)

0(2)

(3)

µs

tVD;DAT

Data valid time(4)

-

-

-

0.93(5)

µs

tSU;DAT

Input transition to clock transition data setup time

250

-

100

-

ns

tSU;STO

Clock high to input high (stop)

4.0

-

0.6

-

µs

tR

Clock and data rise time on load capacitance of 30 pF

-

1000

20

300

ns

tF

Clock and data fall time on load capacitance of 30 pF

-

300

20 x

(VDD/5.5 V)

300

ns

1. Repeated start not supported.

2. The device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the

falling edge of SCL.

3. The maximum tHD;DAT could be 3.45 µs and 0.9 µs for standard mode and fast mode, but must be less than the maximum of

tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW)

of the SCL signal. If the clock stretches the SCL signal, the data must be valid by the setup time before it releases the clock.

4. tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

5. The I²C specification value is 0.9 µs.

Figure 19. AC clock and data timings

START

SDA

I2C bus

R

VCC

VCC

MCU

SDA

SCL

tF

tF

tR

tR

SCL

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

START REPEATED

START

tSU;STO

tSU;STA

STOP

tBUF

R

STSAFE-A120

Electrical characteristics

DS14609 - Rev 1

page 23/38