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DSPIC30F2012AT20E/ML Datasheet(PDF) 198 Page - Microchip Technology |
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DSPIC30F2012AT20E/ML Datasheet(HTML) 198 Page - Microchip Technology |
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198 / 205 page  dsPIC30F2011/2012/3012/3013 DS70139E-page 196 © 2006 Microchip Technology Inc. Power-on Reset (POR) ............................................. 119 Power-up Timer (PWRT) .......................................... 119 Reset Sequence.................................................................. 65 Reset Sources ............................................................ 65 Reset Sources Brown-out Reset (BOR) .............................................. 65 Illegal Instruction Trap................................................. 65 Trap Lockout ............................................................... 65 Uninitialized W Register Trap ..................................... 65 Watchdog Time-out..................................................... 65 Reset Timing Characteristics ............................................ 161 Reset Timing Requirements.............................................. 161 Run-Time Self-Programming (RTSP) ................................. 47 S Simple Capture Event Mode ............................................... 81 Buffer Operation.......................................................... 82 Hall Sensor Mode ....................................................... 82 Prescaler ..................................................................... 81 Timer2 and Timer3 Selection Mode ............................ 82 Simple OC/PWM Mode Timing Requirements.................. 167 Simple Output Compare Match Mode................................. 86 Simple PWM Mode ............................................................. 86 Input Pin Fault Protection............................................ 86 Period.......................................................................... 87 Software Simulator (MPLAB SIM)..................................... 142 Software Stack Pointer, Frame Pointer............................... 18 CALL Stack Frame...................................................... 37 SPI Module.......................................................................... 89 Framed SPI Support ................................................... 90 Operating Function Description .................................. 89 Operation During CPU Idle Mode ............................... 91 Operation During CPU Sleep Mode ............................ 91 SDOx Disable ............................................................. 90 Slave Select Synchronization ..................................... 91 SPI1 Register Map ...................................................... 92 Timing Characteristics Master Mode (CKE = 0) .................................... 168 Master Mode (CKE = 1) .................................... 169 Slave Mode (CKE = 1) .............................. 170, 171 Timing Requirements Master Mode (CKE = 0) .................................... 168 Master Mode (CKE = 1) .................................... 169 Slave Mode (CKE = 0) ...................................... 170 Slave Mode (CKE = 1) ...................................... 172 Word and Byte Communication .................................. 90 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 1 ...................... 128 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 2 ...................... 128 Status Register.................................................................... 18 Symbols Used in Opcode Descriptions............................. 134 System Integration Register Map............................................................. 132 T Table Instruction Operation Summary ................................ 47 Temperature and Voltage Specifications AC ............................................................................. 155 DC ............................................................................. 145 Timer 2/3 Module ................................................................ 75 Timer1 Module .................................................................... 71 16-bit Asynchronous Counter Mode ........................... 71 16-bit Synchronous Counter Mode ............................. 71 16-bit Timer Mode ....................................................... 71 Gate Operation ........................................................... 72 Interrupt ...................................................................... 72 Operation During Sleep Mode .................................... 72 Prescaler .................................................................... 72 Real-Time Clock ......................................................... 72 Interrupts ............................................................ 73 Oscillator Operation............................................ 73 Register Map .............................................................. 74 Timer2 and Timer3 Selection Mode.................................... 86 Timer2/3 Module 16-bit Timer Mode....................................................... 75 32-bit Synchronous Counter Mode ............................. 75 32-bit Timer Mode....................................................... 75 ADC Event Trigger...................................................... 78 Gate Operation ........................................................... 78 Interrupt ...................................................................... 78 Operation During Sleep Mode .................................... 78 Register Map .............................................................. 79 Timer Prescaler .......................................................... 78 Timing Characteristics A/D Conversion Low-speed (ASAM = 0, SSRC = 000) .............. 180 Bandgap Start-up Time............................................. 162 CAN Module I/O........................................................ 177 CLKOUT and I/O ...................................................... 160 External Clock........................................................... 155 I2C Bus Data Master Mode..................................................... 173 Slave Mode....................................................... 175 I2C Bus Start/Stop Bits Master Mode..................................................... 173 Slave Mode....................................................... 175 Input Capture (CAPX)............................................... 165 OC/PWM Module...................................................... 167 Oscillator Start-up Timer........................................... 161 Output Compare Module .......................................... 166 Power-up Timer ........................................................ 161 Reset ........................................................................ 161 SPI Module Master Mode (CKE = 0).................................... 168 Master Mode (CKE = 1).................................... 169 Slave Mode (CKE = 0)...................................... 170 Slave Mode (CKE = 1)...................................... 171 Type A, B and C Timer External Clock ..................... 163 Watchdog Timer ....................................................... 161 Timing Diagrams PWM Output Timing ................................................... 87 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ........................................ 126 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ........................................ 126 Time-out Sequence on Power-up (MCLR Tied to VDD)...................................................... 126 Timing Diagrams and Specifications DC Characteristics - Internal RC Accuracy............... 158 Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion Low-speed ........................................................ 181 Bandgap Start-up Time............................................. 162 Brown-out Reset ....................................................... 161 CAN Module I/O........................................................ 177 CLKOUT and I/O ...................................................... 160 External Clock........................................................... 156 I2C Bus Data (Master Mode) .................................... 174 I2C Bus Data (Slave Mode) ...................................... 175 |
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