1996 Oct 10

7

Philips Semiconductors

Product specification

1.3 GHz universal bus-controlled

TV synthesizer

TSA5520; TSA5521

Table 2

Bus format selection

Table 3

Table 4

Description of Table 3

PIN

NAME

3-WIRE BUS MODE

11

SW

open or HIGH

LOW

13

SCL

clock input

SCL input

14

SDA

data input

SDA input/output

15

CE

chip enable input

address selection input

BYTE

MSB

DATA BYTE

LSB

SLAVE ANSWER

Address Byte (ADB)

1

1

0

0

0

MA1

MA0

0

A

Divider Byte 1 (DB1)

0

N14

N13

N12

N11

N10

N9

N8

A

Divider Byte 2 (DB2)

N7

N6

N5

N4

N3

N2

N1

N0

A

Control Byte (CB)

1

CP

T2

T1

T0

RSA

RSB

OS

A

Band switch Byte (BB)

XXXX

BS4

BS3

BS2

BS1

A

SYMBOL

DESCRIPTION

A

acknowledge

MA1 and MA0

programmable address bits (see Table 5)

N14 to N0

programmable divider bits; N = N14

CP

charge-pump current; CP = 0 = 60

µA; CP = 1 = 280 µA

T2 to T0

test bits (see Table 6); for normal operation T2 = 0, T1 = 0 and T0 = 1

RSA and RSB

reference divider ratio select bits (see Table 7)

OS

tuning amplifier control bit; for normal operation OS = 0 and tuning voltage is ON;

when OS = 1 tuning voltage is OFF (high impedance)

BS4 to BS1

X

don’t care

Table 5

VOLTAGE APPLIED TO THE

CE INPUT (SW = LOW)

MA1

MA0

00

Always valid

0

1

10

11