14

DS786A1

CS4412A

When the device is configured for ramping (RAMP set high) and RST12 or RST34 is set low, the corre-

sponding outputs will begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking

capacitor to discharge.

The ramp feature is intended for use with half-bridge outputs. For “2.1 channel” applications with stereo

half-bridge and mono full-bridge (CNFG[2:0] = 001 or 101), the ramp will only be applied to OUT1 and

OUT2 (the half-bridge channels); OUT3 and OUT4 (the full-bridge channel) will not ramp.

The ramp feature requires a 33 nF capacitor on the RAMP_CAP pin to VP. For applications that do not

enable the ramping feature, RAMP_CAP can be connected directly to VP.

It is not necessary to complete a ramp-up/down sequence before ramping up/down again.

4.2.2

Initial Pulse Edge Delay

After RST12 or RST34 is released, the CS4412A will continue to hold the corresponding power output

pins in a high-impedance state until a pulse edge is sensed on a corresponding PWM input pin. This is

done to prevent a possible DC output condition on the speakers if the PWM inputs are not yet modulating

immediately following the release of the corresponding reset signal. This initial transition delay is indepen-

dent for each input/output pin pair; each output corresponding to an inactive input will remain in a high-

impedance state until its input receives a pulse edge even if other inputs are activated. The pulse edge

must be from a digital low state to a digital high state. Once a pulse edge is detected, the corresponding

output pin will activate and switch as dictated by the output mode configuration as described in section

4.3 on page 15 until either an error condition is detected or until its reset pin is set low.

If the outputs are configured for ramping the CS4412A will perform a ramp-up sequence on OUT1/2 im-

mediately following the release of RST12 and a ramp sequence on OUT3/4 immediately following the re-

lease of RST34. See section 4.2.1 on page 13 for more information on output ramping. If a pulse edge is

detected on an input before the ramp-up sequence finishes on its corresponding output pin, the CS4412A

will continue the ramp sequence and begin normal output operation immediately following its completion.

If a pulse edge is not detected on an input by the time the ramp-up sequence has finished on its corre-

sponding output pin, the output pin will be placed into and remain in a high-impedance state until a pulse

edge is detected on the corresponding input.

4.2.3

Recommended Power-Up Sequence

1. Turn on the system power.

2. Hold RST12 and RST34 low until the power supply is stable. In this state, all associated outputs are

held in a high-impedance state.

3. Release RST12 and RST34 high.

4. Start the PWM modulator output.

4.2.4

Recommended Power-Down Sequence

1. Mute the logic-level PWM inputs present on IN1 - IN4 by applying 50 % duty-cycle input signals.

2. Hold RST12 and RST34 low.

3. Power down the remainder of the system.