STAC9752A datasheet(39/106 Pages) IDT

39 / 106 page

STAC9752A/9753A

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

PC AUDIO

IDT™

STAC9752A/9753A

V 1.5 1206

AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK

AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97

CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit

position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the

AC‘97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transi-

tions and subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 18. Start of an Audio Input Frame

SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for

assigned and/or unassigned time slots) stuffed with 0s by the AC‘97 CODEC. SDATA_IN data is

sampled on the falling edges of BIT_CLK.

5.4.1.

Slot 0: TAG

Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97

CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that

the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deasser-

tion of power on reset for example, while the AC‘97 CODEC’s voltage references settle. When the

AC-Link “CODEC Ready” indicator bit is a 1 it indicates that the AC-Link and AC‘97 CODEC control

and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within

400

µs after it starts receiving valid SYNC pulses from the controller, to provide indication of connec-

tion to the link and Control/Status registers are available for access. The AC’97 Controller and

related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set

SYNC

BIT_CLK

SDATA_IN

slot1

slot2

End of previous audio frame

slot(12)

"0"

Data Phase

20.8 uS (48 kHZ)

Tag Phase

12.288 MHz

Time Slot "Valid" Bits

Slot 1

Slot 2

Slot 3

Slot 12

("1" = time slot contains valid PCM data)

valid

"0"

Frame

"0"

SYNC

BIT_CLK

SDATA_IN

slot1

slot2

End of previous audio frame

Codec

Ready

SYNC

detected

first

SDATA_OUT

bit of frame

STAC9752A Datasheet(PDF) 39 Page - Integrated Device Technology

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