Nexperia

NEX8080 series

Wide Vcc range multi-mode flyback controller

S

Q

R

Q

1/KFB

CFB

FB_int

RS

DRV

RFB

FB

VFB_OPEN

CS

Rd

CF

RBOT

RTOP

VO

RL

CO

n:1

aaa-040378

Fig. 16. Typical circuit of voltage control

9.3.7. Multimode operation

NEX8080x is a multi-mode PWM controller implemented with peak current mode control. As the load changes, it

automatically switches between CCM, QR, DCM PFM modes. To maintain a high efficiency across the entire load range,

turning on the primary MOS is always gated by the CLK signal, which is the clamping frequency commanded by FB voltage.

Under heavy load and low line conditions, FB is high, which means the primary peak current and clamp frequency is high.

Since a longer time is needed for demagnetization, the clock signal (CLK) arrives before demagnetization, so the power

MOS will be turned on by the clock. At this moment, the magnetizing inductor current is not reset to zero yet, converter

works in CCM.

As the load decreases, or line voltage increases, FB voltage will decrease, which means the primary peak current and clamp

frequency decreases. Demagnetization can be finished before the clock signal. In this condition, the power MOS will not

be turned on until the clock signal and the following valley moment are detected, (see Fig. 17 and Section 9.3.10). In this

way, power MOS turn on at the first valley after clock, the converter works in either QR/DCM (if clamp frequency is still at

maximum frequency) or PFM (if clamp frequency already be lower than maximum value).

If the load continues to decrease, the clamp frequency further decreases as FB voltage decreases. The ringing amplitude

at auxiliary winding may be damped too small for a valley moment to be detected after clock arrives. In this case, once the

tW_VALLEY time expires after CLK, the primary MOS will be forced on.

9.3.8. Burst mode control

As the load decreases, FB voltage will decrease to regulate the output voltage. As a result, the peak-control voltage (equal

to the peak voltage of CS) decreases and is finally clamped at its minimum limit (typically ~90 mV). Meanwhile, the switching

frequency also decreases and is clamped at FMIN (typically 25 kHz) to avoid audible noise. If the load decreases further,

FB voltage will drop below the VFB_BURST_OFF threshold (typically 0.3 V) and DRV pulse is disabled. In this burst-off period,

VCC current drops to IBURST (typically 270 μA). At this moment, since no power is being delivered to the output anymore, the

output voltage begins decrease. The voltage control loop will increase FB voltage gradually. Once FB voltage is higher than

VFB_BURST_ON threshold (typically 0.35 V), the DRV pulse is resumed. Using this method of burst mode control improves the

light load efficiency significantly.

9.3.9. ZCD voltage detection

During the flyback period, the information of output voltage can be derived by sampling ZCD voltage as shown in Fig. 17.

NEX8080_series

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Product data sheet

Rev. 1 — 30 September 2024

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