Nexperia

NEX8080 series

Wide Vcc range multi-mode flyback controller

ZCD

Auxiliary

winding

aaa-040379

DRV

tZCD_SAMPLE

Sample at here

Valley moment

(VO + Vf) × NAUX/NSEC

(VO + Vf) × NAUX/NSEC × RZB/(RZT + RZB)

Fig. 17. ZCD voltage detection and valley detection

The output voltage OVP and UVP/SCP protection are implemented by comparing the sampled ZCD voltage with different

threshold voltages.

The output voltage OVP protection is triggered if the sampled ZCD voltage is higher than OVP threshold for seven

consecutive cycles.

The output voltage short-circuit protection (SCP) is triggered if the sampled ZCD voltage is lower than SCP threshold

VZCD_SCP (typically 0.3 V) for seven consecutive cycles.

Since the output voltage need time to setup, the UVP/SCP protection is disabled for a tBLK_UVP blanking time during soft

start.

Due to the leakage inductance of the transformer, there is large ringing waveform at ZCD pin at the beginning of the flyback

period. To avoid sampling at this ringing moment, a blanking time is added after the going-low of DRV signal. ZCD sampling

is not allowed until this blanking window expires.

9.3.10. Valley switching

During QR/DCM/PFM mode, once the magnetizing current decreases to zero, the primary inductor begins oscillating with

the parasitic capacitor of the primary MOS. It is ideal to turn on the primary MOS at the valley moment of oscillation to

minimize the switching loss. As shown in Fig. 17, when the auxiliary winding voltage becomes negative, ZCD pin is clamped

at ~0 V internally, and the current flowing out of ZCD pin is detected. Once the current is larger than IZCD_VALLEY (~9 μA),

that moment is identified as a valley moment. Several valley moments may be identified before CLK signal arrives. The

valley moment just behind CLK is chosen as the moment to turn on the primary MOS.

9.3.11. Oscillator frequency

The NEX8080x is specially designed for wide output voltage range applications. To optimize the efficiency of each output

voltage condition, the maximum switching frequency is adjusted according to the target output voltage, as derived by ZCD

detection. Different frequency-vs-FB curves are used for different output voltage conditions.

As FB voltage decreases, the clamp frequency CLK will decrease until it arrives the minimum limit FMIN (typically 25 kHz, to

avoid audible noise), thus a relatively high efficiency is achieved in the whole load range.

NEX8080_series

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Product data sheet

Rev. 1 — 30 September 2024

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