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PIC16F72 Datasheet(PDF) 5 Page - Microchip Technology |
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PIC16F72 Datasheet(HTML) 5 Page - Microchip Technology |
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5 / 14 page ![]() 2002 Microchip Technology Inc. Preliminary DS39588A-page 5 PIC16F72 2.3.1.1 Load Configuration After receiving the Load Configuration command, the PC will be set to 0x2000 and the data sent with the command is discarded. The four ID locations and the configuration word can then be programmed using the normal programming sequence, as described in Section 2.3. A description of the memory mapping schemes of the program memory for normal operation and Configuration mode operation is shown in Figure 2-1. After the configuration memory is entered, the only way to get back to the user program memory is to exit the Program/Verify Test mode by taking MCLR low. 2.3.1.2 Load Data for Memory The device will load in a 14-bit “data word” when 16 cycles are applied, as described previously. A timing diagram for the load data command is shown in Figure 5-1. 2.3.1.3 Read Data from Memory The device will transmit data bits out of the memory (program or configuration) currently addressed by the PC, starting with the second rising edge of the clock input. RB7 will go into Output mode on the second ris- ing clock edge and will revert back to Input mode (hi-impedance) after the 16th rising edge. A timing dia- gram for this command is shown in Figure 5-2. If the device is code protected, user program memory will read all ‘0’s. Configuration memory can still be read. 2.3.1.4 Increment Address The PC is incremented by one. A timing diagram for this command is shown in Figure 5-3. 2.3.1.5 Begin Programming A ‘Load Data’ command must be issued before every ‘Begin Programming’ command. Program- ming of memory (configuration or program) will begin after this command is received and decoded. Program- ming requires (tprog) time and is terminated using an ‘End Programming’ command. 2.3.1.6 Chip Erase (Program Memory) Erasure of configuration and program memory begins after this command is received and decoded. The erase sequence is self-timed and it is not necessary to issue an ‘End Programming’ command, only to wait for the appropriate time interval (tera) for the entire erase sequence, before issuing another command. This procedure will disable code protection (code pro- tect bit = 1); however, all data within the program mem- ory will be erased when this command is executed and thus, the security of the data or code is not compromised. 2.4 Programming Algorithm Requires Variable VDD The PIC16F72 uses an intelligent algorithm, which calls for program verification at VDDAPP. The actual chip erase and programming must be done with VDD in the VDDP range (see Table 5-1). VDDP =VDD range required during programming VDDAPP =VDD in the target application Programmers must verify the PIC16F72 at VDDAPP. Since Microchip may introduce future versions of the PIC16F72 with a broader VDD range, it is best that these levels are user selectable (defaults are OK). Note: All CHIP ERASE operations must take place with VDD between 4.75V and 5.25V. Note: Any programmer not meeting this require- ment may only be classified as a “proto- type” or “development” programmer, but not a “production quality” programmer. |
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