PSvfBGA

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Process Highlights

Die thickness (max)

Bond pad pitch (min)

Marking

Laser

Wafer thinning

200 & 300 mm wafers

Standard Materials

Package substrate

-

Conductor

Copper

-

Dielectric

Thin core FR5 or equivalent

Die attach adhesive

Conductive or non conductive

Encapsulant

Epoxy mold compound

Solder ball

Eutectic SnPb / Pb free

Test Services

Program Generation / Conversion

Product Engineering

Wafer sort

256 Pin x 20 MHz test system available

Shipping

JEDEC trays

Tape and Reel services

PSvfBGA Cross Section

Footprint - top (B)

Footprint - bottom (C)

Package size (A)

0.27mm

Max die size (D)

(E)

LAMINATE

data sheet

PSvfBGA Top View

AB

C

D

E

Body

Package Interconnect

Bottom Package

Package Interconnect ball

Typical Wirecount

Size (mm)

Matrix Ball Count

Ball Count

Die Size (mm) center to package edge (mm) for given package size

10

15

104

300

<5.50

0.450

320

11

16

112

350

<6.00

0.625

360

12

18

128

400

<7.50

0.475

420

13

19

136

450

<8.00

0.650

460

14

21

152

550

<9.00

0.500

520

15

22

160

700

<10.00

0.675

600

• Dimensions are in line with JEDEC JC-11

standards for PoP packages in

development

• Assuming 2 perimeter rows of

interconnects at 0.65 mm pitch

• Assuming 4 perimeter rows of BGA

balls to motherboard at 0.50 mm pitch

Package on Package (P0P) Family

Contact Amkor for Daisy chain sample availability, the

latest PSvfBGA capabilities, and for full review of

PSvfBGA, PoP technology and roadmaps.