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CF5762AB0 Datasheet(PDF) 6 Page - Nippon Precision Circuits Inc

Part # CF5762AB0
Description  Analog Chime Clock CMOS IC
PDF  10 Pages
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Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

CF5762AB0 Datasheet(HTML) 6 Page - Nippon Precision Circuits Inc

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CF5762AB0
NIPPON PRECISION CIRCUITS INC.—6
Chattering Elimination
Power-ON Initialization
When power is applied, the following reset functions
take place.
I
Clock movement motor outputs (O1, O2)
After the oscillator starts, each output is activated
with O1 being LOW and O2 being HIGH.
I
Reset (RESET)
After power is applied, a 62.5ms reset pulse is out-
put. If, however, RESET is HIGH when power is
applied, the corresponding reset state is recog-
nized as-is.
I
Melody trigger (MT)
If MT is HIGH when power is applied, melody
output stops. Melody output starts when MT goes
LOW and then goes HIGH again.
I
Time information (S1 to S4)
The time data is reset to a zero state not represent-
ing any hour in the range 1 to 12 o’clock, and the
inputs are not read until the next hourly signal
input.
I
Melody switching function (SEL1, SEL2)
When power is applied, the input states are reset
and then immediately read in.
I
Melody stop at night (AMI, PMI)
When power is applied, the PM flag is set to LOW
(AM setting) and then, immediately, the input
states are read in. If at this time both AMI and PMI
are HIGH, then the PM flag stays set to LOW.
Input
Description
S1 to S4, CDS, WSEL
No chattering elimination function
MT, RESET
If the input goes HIGH and continues for 2 or more 16Hz cycles, then the input is recognized, otherwise it is ignored.
If the input goes LOW, it is sampled at 16Hz.
AMI, PMI
If the input changes state and continues for 2 or more 16Hz cycles, then the input is recognized, otherwise it is ignored.
SEL1, SEL2
The inputs are sampled periodically at 16Hz. If either SEL1 or SEL2 changes state, the state is held for 62.5ms and then
the state of both SEL1 and SEL2 are read. If either SEL1 or SEL2 changes state during this interval, a further interval of
62.5ms is added before reading the input states (see figure 2).
Figure 2. SEL1, SEL2 read timing
16Hz
SEL1
SEL2
62.5ms 62.5ms
62.5ms 62.5ms 62.5ms
Read hold pulse
Status read clock



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