SN54ACT8990, SN74ACT8990

TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

SCAS190E – JUNE 1990 – REVISED JANUARY 1997

4

POST OFFICE BOX 655303

Table 1. Terminal Assignments

TERMINAL

TERMINAL

TERMINAL

TERMINAL

NO.

NAME

NO.

NAME

NO.

NAME

NO.

NAME

A2

NC

B10

NC

F11

NC

K6

NC

A3

ADRS4

B11

NC

G1

DATA5

K7

VCC

A4

NC

C1

DATA2

G2

NC

K8

DATA15

A5

ADRS1

C2

DATA1

G10

NC

K9

TDI0

A6

ADRS0

C3

NC

G11

TMS1

K10

NC

A7

NC

C10

TMS4/EVENT2

H1

NC

K11

TCKI

A8

INT

C11

TMS5/EVENT3

H2

DATA6

L2

DATA9

A9

RD

D1

DATA4

H10

TDO

L3

NC

A10

TRST

D2

DATA3

H11

TMS0

L4

DATA12

B1

DATA0

D10

TMS3/EVENT1

J1

DATA8

L5

DATA13

B2

NC

D11

NC

J2

DATA7

L6

NC

B3

ADRS3

E1

NC

J10

TCKO

L7

DATA14

B4

ADRS2

E2

GND

J11

NC

L8

TOFF

B5

NC

E10

VCC

K1

NC

L9

TDI1

B6

NC

E11

TMS2/EVENT0

K2

NC

L10

NC

B7

GND

F1

VCC

K3

DATA10

B8

RDY

F2

NC

K4

DATA11

B9

WR

F10

GND

K5

NC

NC – No internal connection

functional block diagram

4

2

2

16

16

16

5

RD

WR

RDY

INT

ADRS(4 – 0)

DATA(15 – 0)†

Host

Interface

Target

Interface

TMS(5 – 2)/

EVENT(3 – 0)†

TMS(1 – 0)

TDI(1 – 0)†

TDO

TOFF†

TCKO

TCKI

TRST †

Event

Block

Sequencer

Block

Counter Block

Command Block

Serial Block

Host

Block

Read Data Bus

Write Data Bus

† Inputs have internal pullup resistors.