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KIT-7101-RK Datasheet(PDF) 3 Page - Arista Networks, Inc

Part # KIT-7101-RK
Description  7130LBR Series Layer 1 Application Switch
PDF  11 Pages
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Manufacturer  ARISTA [Arista Networks, Inc]
Direct Link  https://www.arista.com/en/
Logo ARISTA - Arista Networks, Inc

KIT-7101-RK Datasheet(HTML) 3 Page - Arista Networks, Inc

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High Availability and Flexibility
The Arista 7130LBR Series were designed for exible deployment and continuous operations with system wide monitoring of both
hardware and software components, simple serviceability and provisioning to prevent single points of failure.
Key features include:
• AC and DC power supply options
• Front to Rear cooling with dynamic temperature control.
• Redundant, color coded, eld serviceable power and cooling subsystems:
• 1+1 hot-swappable platinum rated power supplies
• N+1 hot-swappable fans
• Live software patching
• Self healing software with Stateful Fault Repair (SFR)
7130LBR Series | Platform Overview
Data Sheet
Custom Applications & FPGA Development Kit
FPGA developers can write custom applications for the 7130LBR Series with Arista’s FPGA Development Kit (FDK). The FDK includes API
documentation, sample code, and IP cores to streamline development. Arista development toolkits enable complete and unfettered
access to the facilities provided by the in-system FPGAs.
Precision Timing (IEEE 1588v2 and PPS)
To meet the stringent timing and synchronization requirements in nancial markets, telecom, and media & entertainment networks,
Arista’s 7130LBR delivers high precision in-band time and frequency distribution support via Precision Time Protocol (PTP, IEEE 1588v2)
with optional Pulse-Per-Second (PPS) inputs for added accuracy. Leveraging a high stability on-board oscillator, 7130LBRs can achieve
picosecond-level time synchronization.
The 7130LBR features two front-panel SMA PPS inputs, with optional primary/secondary failover for added resiliency. An internal PPS
distribution network delivers PPS signals to each application FPGA. Two front-panel SMA outputs can forward PPS or output the
internal 10Mhz clock to downstream systems.
IP Core
Features
10GbE MAC/PHY
• Ultra low latency 10GbE ethernet PCS/PMA and MAC
• 10GbE & 1GbE support
• AXI4 stream interface
• Register interface for counters and link status
25GbE MAC/PHY
• Ultra low latency 25GbE ethernet PCS/PMA and MAC
• 25GbE support
• AXI4 stream interface
• Register interface for counters and link status
Timestamper
• Complete precision timestamping system
• Includes timestamper core + sync & control daemon
• PPS synchronization
• Example Start-of-Frame timestamping application
Mux
• 10GbE packet multiplexer
• Con gurable scheduling algorithms
• Advanced eXtensible Interface (AXI4) streaming inputs
• Status and packet counters
• Storm control



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