P89V52X2FN datasheet(15/56 Pages) PHILIPS

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P89V52X2_1

Preliminary data sheet

Rev. 01 — 7 June 2007

15 of 56

NXP Semiconductors

P89V52X2

80C51 with 256 B RAM, 192 B data EEPROM

6.7 Flash memory

6.7.1 Flash organization

The P89V52X2 program memory consists of an 8 kB block of user code. The flash can be

read or written in bytes but may only be erased as an entire block. A chip erase function

will erase the entire user code memory and its associated security bits. This flash memory

can be erased or programmed using a programmer tool that supports ICP.

6.7.2 Features

• Flash internal program memory

• Programming and erase over the full operating voltage range.

• Programming with industry-standard commercial programmers.

• 10000 typical erase/program cycles for each byte.

• 100 year minimum data retention.

6.8 Timers/counters 0 and 1

The two 16-bit Timer/Counter registers: Timer 0 and Timer 1 can be configured to operate

either as timers or event counters (see Table 10 and Table 11).

In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can

think of it as counting machine cycles. Since a machine cycle consists of six oscillator

periods, the count rate is 1

⁄

6 of the oscillator frequency.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its

corresponding external input pin, T0 or T1. In this function, the external input is sampled

once every machine cycle.

When the samples show a high in one cycle and a low in the next cycle, the count is

incremented. The new count value appears in the register in the machine cycle following

the one in which the transition was detected. Since it takes two machine cycles (12

oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is 1

⁄

12 of

the oscillator frequency. There are no restrictions on the duty cycle of the external input

signal, but to ensure that a given level is sampled at least once before it changes, it

should be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’

selection, Timer 0 and Timer 1 have four operating modes from which to select.

The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the Special Function

selected by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both

Timers/Counters. Mode 3 is different. The four operating modes are described in the

following text.

Table 10.

TMOD - Timer/Counter mode control register (address 89H) bit allocation

Not bit addressable; Reset value: 0000 0000B; Reset source(s): any source

Bit

Symbol

T1GATE

T1C/T

T1M1

T1M0

T0GATE

T0C/T

T0M1

T0M0

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