AD7682 datasheet(13/20 Pages) AD

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Preliminary Technical Data

AD7689

Rev. PrC | Page 13 of 20

CONFIGURATION REGISTER, CFG

The AD7689 uses a 14-bit configuration register (CFG[13:0])

for configuring the inputs, channel to be converted, 1-pole filter

bandwidth, reference, and channel sequencer. The CFG is

latched MSB first with DIN synchronized to SCK rising edge. At

the end of conversion, the register is updated allowing the new

settings to be used. There is always a one deep conversion delay

regardless of when the CFG is written to; during or after

conversion. Note that at power up, the CFG is undefined and a

dummy conversion is required to update the register. To preload

the CFG with a factory setting, hold DIN high for 1 conversion.

Thus CFG[13:0] = 0x3FFF. This sets the AD7689 for:

• IN[7:0] unipolar referenced to GND, sequenced in order

• Full bandwidth for 1-pole filter

• Internal reference/temp sensor disabled, buffer enabled

• No read back of CFG

Table 9 Summarizes the configuration register bit details. Each

corresponding section, where necessary, highlights further

details of the bits used for the specific functions.

Table 9. Configuration Register Description

Bit

Name

Description

CFG

0 – Keep current config settings

1 – Overwrite contents of register

12:10

INCC

Input Channel Configuration

Function

Bipolar differential pairs, IN-

referenced to VREF/2

Bipolar, IN0-IN7 referenced to

COM = VREF/2

Temperature sensor

Unipolar differential pairs, IN-

referenced to GND (±100mV)

Unipolar, IN0-IN7 referenced to

COM = GND (±100mV)

Unipolar, IN0-IN7 referenced to

GND (single ended)

9:7

INn

Channel Selection in binary fashion

Function

IN0

IN1

IN7

Selects BW for Low Pass Filter

0 – ¼ of BW

1 – Full BW

5:3

REF

Reference/Buffer Selection

Function

Internal ref, REF = 2.5V output

Internal ref, REF = 4.096V output

External ref, Temp enabled

External ref, internal Buffer,

Temp enabled

External ref, Temp disabled

External ref, internal Buf, Temp

disabled

2:1

SEQ

Channel Sequencer

Function

Disable Sequencer

Update config during sequence

Scan IN0–INn (set in CFG[9:7])

then TEMP

Scan IN0–INn (set in CFG[9:7])

Read back

0 – Read back current configuration at end of data

1- Do not read back contents of configuration

ANALOG INPUTS

Input Configurations

Figure 14 shows the different methods for configuring the

analog inputs with CFG[12:10].

GND

COM

CH0+

CH3+

CH1+

CH2+

CH4+

CH5+

CH6+

CH7+

CH0+

CH3+

CH1+

CH2+

CH4+

CH5+

CH6+

CH7+

COM-

GND

COM

IN1

IN0

IN2

IN3

IN4

IN5

IN6

IN7

IN1

IN0

IN2

IN3

IN4

IN5

IN6

IN7

IN1

IN0

IN2

IN3

IN4

IN5

IN6

IN7

IN1

IN0

IN2

IN3

IN4

IN5

IN6

IN7

A- 8 CHANNELS,

SINGLE ENDED

B - 8 CHANNELS,

COMMON REFERNCE

GND

COM

CH0+ (-)

CH1+ (-)

CH2+ (-)

CH3+ (-)

CH0- (+)

CH1- (+)

CH0+ (-)

CH1+ (-)

CH0- (+)

CH1- (+)

CH2- (+)

CH3- (+)

C - 4 CHANNELS,

DIFFERENTIAL

GND

COM

CH2+

CH3+

CH4+

CH5+

D - COMBINATION

COM-

{

Figure 14. Multiplexed Analog Input Configuraitons

The analog inputs can be configured as:

• Figure 14A, single ended referenced to system ground;

CFG[12:10] = 1112.

• Figure 14B, bipolar differential with a common reference

point, COM, = VREF/2; CFG[12:10] = 0102.

Unipolar differential with COM connected to a ground

sense; CFG[12:10] = 1102.

• Figure 14C, bipolar differential pairs with INx- referenced

to VREF/2; CFG[12:10] = 00X2.

Unipolar differential pairs with INx- referenced to a

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