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AD7689

Preliminary Technical Data

Rev. PrC | Page 18 of 20

WITH BUSY INDICATOR

This mode is usually used when the AD7689 is connected to an

SPI-compatible digital host using an interrupt input. The

connection diagram is shown in Figure 19,, and the

corresponding timing is given in Figure 20.

A rising edge on CNV initiates a conversion and forces SDO to

high impedance. SDO is maintained in high impedance until

the completion of the conversion irrespective of the state of

CNV. Prior to the minimum conversion time, CNV can be

used to select other SPI devices, such as analog multiplexers,

but CNV must be returned low before the minimum conversion

time elapses and then held low for the maximum possible

conversion time to guarantee the generation of the busy signal

indicator.

Configuring the AD7689 for the (n + 1) conversion is initiated

when SCK is high and a rising edge on CNV. After this mode is

initiated, CNV is a don’t care as the CFG word is written in

MSB first with 14 SCK rising edges. As shown in Figure 20,

CFG is written to during the current (n) conversion before the

end of conversion, or tCONV minimum time. At the end of

conversion, the register is updated. In this mode, the new

configuration settings are used for the following (n + 1)

acquisition and conversion. Note that SCK must be high when

CNV goes high for this configuration mode. The AD7689 can

also be configured on the first 14 SCK of the data reading (not

shown), thus reducing the number of SCK bursts. However, this

new CFG setting is for the (n + 2) conversion.

When the conversion is complete, SDO goes from high

impedance to low impedance. With a pull-up on the SDO line,

this transition can be used as an interrupt signal to initiate the

data reading controlled by the digital host. The AD7689 then

enters the acquisition phase and powers down. The data bits are

clocked out, MSB first, by subsequent SCK falling edges. The

data is valid on both SCK edges. Although the rising edge can

be used to capture the data, a digital host using the SCK falling

edge will allow a faster reading rate, provided it has an

acceptable hold time. After the optional 17th SCK falling edge or

when CNV goes high (whichever occurs first), SDO returns to

high impedance.

If multiple AD7689s are selected at the same time, the SDO

output pin handles this contention without damage or induced

latch-up. Meanwhile, it is recommended to keep this contention

as short as possible to limit extra power dissipation.

DATA IN

CFG DATA

CLK

CONVERT

CNV

SCK

SDO

DIN

AD7689

DIGITAL HOST

VIO

IRQ

Figure 19. With Busy Indicator Connection Diagram

D15

D14

D13

tDIS

SCK

tSCK

tSCKL

tSCKH

tHSDO

tDSDO

tSDIN

tHDIN

tCSCK

CONVERSION

(n)

CONVERSION

(n + 1)

ACQUISITION

(n)

ACQUISITION

(n + 1)

(MAX)

CONV

(MIN)

CONV

t CYC

tACQ

CNV

DIN

SDO

C13

C12

C11

Figure 20. Wwith Busy Indicator Serial Interface Timing

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