S5335 datasheet(3/189 Pages) AMCC

3 / 189 page

S5335 – PCI Bus Controller, 3.3V

Revision 5.01 – November 30, 2005

AMCC Confidential and Proprietary

DS1657

Data Sheet

TABLE OF CONTENTS

FEATURES .............................................................................................................................................................. 2

APPLICATIONS ...................................................................................................................................................... 2

DESCRIPTION ........................................................................................................................................................ 2

TABLE OF CONTENTS .......................................................................................................................................... 3

LIST OF FIGURES .................................................................................................................................................. 8

LIST OF TABLES .................................................................................................................................................. 11

S5335 ARCHITECTURE ....................................................................................................................................... 13

S5335 Register Architecture ............................................................................................................................ 13

PCI Configuration Registers ............................................................................................................................ 13

PCI Operation Registers .................................................................................................................................. 14

Add-On Bus Operation Registers .................................................................................................................... 14

Non-Volatile Memory Interface ........................................................................................................................ 14

Mailbox Operation ........................................................................................................................................... 15

Pass-Thru Operation ....................................................................................................................................... 17

FIFO PCI Bus Mastering Operation ................................................................................................................. 17

Signal Type Definition ...................................................................................................................................... 19

NON-VOLATILE MEMORY INTERFACE SIGNALS ............................................................................................ 23

ADD-ON BUS INTERFACE SIGNALS .................................................................................................................. 24

PCI CONFIGURATION REGISTERS .................................................................................................................... 27

Vendor Identification Register (VID) ................................................................................................................ 29

Device Identification Register (DID) ................................................................................................................ 30

PCI Command Register (PCICMD) ................................................................................................................. 31

PCI Status Register (PCISTS) ......................................................................................................................... 33

Revision Identification Register (RID) .............................................................................................................. 35

Class Code Register (CLCD) .......................................................................................................................... 36

Cache Line Size Register (CALN) ................................................................................................................... 40

Latency Timer Register (LAT) ......................................................................................................................... 41

Header Type Register (HDR) .......................................................................................................................... 42

Built-In Self-test Register (BIST) ..................................................................................................................... 43

Base Address Registers (BADR) ..................................................................................................................... 44

Determining Base Address Size ...................................................................................................................... 44

Assigning the Base Address ............................................................................................................................ 44

Expansion ROM Base Address Register (XROM) .......................................................................................... 49

Interrupt Line Register (INTLN) ....................................................................................................................... 51

Interrupt Pin Register (INTPIN) ....................................................................................................................... 52

Minimum Grant Register (MINGNT) ................................................................................................................ 53

Maximum Latency Register (MAXLAT) ........................................................................................................... 54

Outgoing Mailbox Registers (OMB) ................................................................................................................. 56

Incoming Mailbox Registers (IMB) ................................................................................................................... 56

FIFO Register Port (FIFO) ............................................................................................................................... 56

PCI Controlled Bus Master Write Address Register (MWAR) ......................................................................... 57

PCI Controlled Bus Master Write Transfer Count Register (MWTC) ............................................................... 58

PCI Controlled Bus Master Read Address Register (MRAR) .......................................................................... 59

PCI Controlled Bus Master Read Transfer Count Register (MRTC) ............................................................... 60

Mailbox Empty Full/Status Register (MBEF) ................................................................................................... 61

Interrupt Control/Status Register (INTCSR) .................................................................................................... 63

Master Control/status Register (MCSR) .......................................................................................................... 67

ADD-ON BUS OPERATION REGISTERS ............................................................................................................ 70

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