CAT25010LET3 datasheet(5/17 Pages) CATALYST

5 / 17 page

CAT25010, CAT25020, CAT25040

Doc. No. MD-1006 Rev. T

Characteristics subject to change without notice

STATUS REGISTER

The Status Register, as shown in Table 2, contains a

number of status and control bits.

The RDY

¯¯¯¯ (Ready) bit indicates whether the device is

busy with a write operation. This bit is automatically

set to 1 during an internal write cycle, and reset to 0

when the device is ready to accept commands. For

the host, this bit is read only.

The WEL (Write Enable Latch) bit is set/reset by the

WREN/WRDI commands. When set to 1, the device is

in a Write Enable state and when set to 0, the device

is in a Write Disable state.

The BP0 and BP1 (Block Protect) bits determine

which blocks are currently write protected. They are

set by the user with the WRSR command and are

non-volatile. The user is allowed to protect a quarter,

one half or the entire memory, by setting these bits

according to Table 3. The protected blocks then

become read-only.

Table 2. Status Register

BP1

BP0

WEL

RDY

¯¯¯¯

Table 3. Block Protection Bits

Status Register Bits

BP1

BP0

Array Address Protected

Protection

None

No Protection

CAT25010: 060-07F

CAT25020: 0C0-0FF

CAT25040: 180-1FF

Quarter Array Protection

CAT25010: 040-07F

CAT25020: 080-0FF

CAT25040: 100-1FF

Half Array Protection

CAT25010: 000-07F

CAT25020: 000-0FF

CAT25040: 000-1FF

Full Array Protection

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