3

9/20/2004

Supertex, Inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 222-8888 FAX: (408) 222-4895 www.supertex.com

HV9906

Pinout

1

2

3

45

6

7

8

HV9906

+Vin

Vdd

AGND

PS

GATE

Von

PGND

NS

Pin Description

supply pin for the internal circuits. It must be bypassed with a low

ESR capacitor to provide a low impedance path for the gate drive

and be capable of storing sufficient energy so that the voltage does

not decay below the UVLO threshold during the time when the

input voltage is below the minimum required by the regulator.

AGND – This pin is the common connection for analog circuits.

GATE – This pin is the output for driving the gate of an external N-

channel MOSFET.

PGND – This is the common connection for the GATE drive circuit.

NS – This pin is the negative terminal of the differential sense

feedback circuit.

PS – This pin is the positive terminal of the differential sense

feedback circuit.

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Functional Block Diagram

VCO

C

C

Delay

Delay

High Voltage

Regulator

UVLO

and

POR

Bandgap

Reference

+Vin

Von

Vdd

AGND

GATE

PGND

Reset Pulse

Sample Pulse

Vdd

Vdd

1V

1V

1V

Vdd

Vref

Q

R

S

Vref

Q

_

NS

PS

Driver