HT46RB50 datasheet(15/53 Pages) HOLTEK

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HT46RB50

Rev. 1.20

November 1, 2006

Timer/Event Counter

Two Timer/Event Counters (TMR0, TMR1) are imple-

mented in the microcontroller. The Timer/Event Counter

0 contains a 8-bit programmable count-up counter and

the clock may come from an external source or an inter-

nal clock source. An internal clock source comes from

fSYS. The Timer/Event Counter 1 contains a 16-bit pro-

grammable count-up counter and the clock may come

from an external source or an internal clock source. An

internal clock source comes from fSYS/4. The external

clock input allows the user to count external events,

measure time intervals or pulse widths, or generate an

accurate time base.

There are five registers related to the Timer/Event

Counter 0; TMR0 (0DH), TMR0C (0EH) and the

Timer/Event Counter 1; TMR1H (0FH), TMR1L (10H),

TMR1C (11H). For 16bits timer to Write data to TMR1L

will only put the written data to an internal lower-order

byte buffer (8-bit) and writing TMR1H will transfer the

specified data and the contents of the lower-order byte

buffer to TMR1H and TMR1L registers. The Timer/Event

Counter 1 preload register is changed by each writing

TMR1H operations. Reading TMR1H will latch the con-

tents of TMR1H and TMR1L counters to the destination

and the lower-order byte buffer, respectively. Reading

the TMR1L will read the contents of the lower-order byte

buffer. The TMR0C (TMR1C) is the Timer/Event Coun-

ter 0 (1) control register, which defines the operating

mode, counting enable or disable and an active edge.

The T0M0, T0M1 (TMR0C) and T1M0, T1M1 (TMR1C)

bits define the operation mode. The event count mode is

used to count external events, which means that the

clock source is from an external (TMR0, TMR1) pin. The

timer mode functions as a normal timer with the clock

source coming from the internal selected clock source.

Finally, the pulse width measurement mode can be used

to count the high or low level duration of the external sig-

nal (TMR0, TMR1), and the counting is based on the in-

ternal selected clock source.

In the event count or timer mode, the timer/event coun-

ter starts counting at the current contents in the

timer/event counter and ends at FFFFH(for 16 bits timer

is FFFFH, bit 8 bits timer will be FFH). Once an overflow

occurs, the counter is reloaded from the timer/event

counter preload register, and generates an interrupt re-

quest flag (T0F; bit 5 of the INTC0, T1F; bit 6 of the

INTC0).

T M 1

T M 0

T M R 0

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

T 0 D 2 ~ T 0 D 0

( 6 + 2 ) o r ( 7 + 1 )

C o m p a r e

P W M

T o P D 0 / P D 1 C i r c u i t

8 - B i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

8 - B i t T i m e r / E v e n t C o u n t e r

( T M R 0 )

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

Timer/Event Counter 0

T M 1

T M 0

T M R 1

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

f S Y S / 4

f I N T

1 6 - B i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

1 6 - B i t T i m e r / E v e n t C o u n t e r

( T M R 1 H / T M R 1 L )

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

Timer/Event Counter 1

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