POWER MANAGEMENT

SC2615

7

 2003 Semtech Corp.

www.semtech.com

Description

The Semtech SC2615 DDR power supply controller is

the latest and most complete linear regulator, providing

the necessary functions to comply with the BF_CUT signal

signal is generated via an External “Glue Chip” and can

be logically defined as :

BF_CUT=S0 .NAND.P_OK

Where S0 is the “Motherboard Active signal”. When S0

is logic “Low”, the motherboard is in S3 mode. The

Latched BF_CUT signal is the input to the SC2615

controller, and is generated by using the S5 signal. All

references made to BF_CUT are referring to the latched

signal.

The BF_CUT signal is inverted to externally drive a

Back_Feed_Cut MOSEFT, used to prevent current flow

from the VDDQ supply back to the 3.3V supply during S3

state.

VDDQ supply and the VTT termination voltages

are supplied to the DDR SDRAM databus during S0

(normal operation) state. During S0, VDDQ is supplied

via the an external pass MOSFET from the 3.3V rail ,

sourcing high output currents to the VDD bus as well as

supplying the termination supply current.

The VTT termination voltage is an internal sink/source

linear regulator, which during S0 state receives its power

from the VDDQ bus. It is capable of sourcing and sinking

1.8 Amps (Min) . The current limit on this pin is set to 3

Amps (typical). The current handling capacity of this pin

depends upon the amount of heat the PC board can sink

from

the SC2615 thermal pad. (See mounting

instructions). The PC board layout must take into

consideration the high current paths, and ground returns

for both the VDDQ and VTT supply pins. VTT, LGND, VDDQ,

3.3VCC traces must also be routed using wide traces to

minimize power loss and heat in these traces, based on

the current handling requirements.

S3 and S5 States

The operation of the VDDQ and VTT supplies is governed

by the internal sequencing logic in strict adherence with

The timing diagram demonstrates the state of the

controller, and each of the VDDQ and VTT supplies during

S3 and S5 transitions. When S3 is low, the VDDQ internal

regulator supplies the “Suspend To RAM” current of 650

mA (max) to maintain the information in memory while in

standby mode. Since the Memory read/write cycles are

suspended during S3, the VTT termination voltage is not

needed and is tri-stated during S3. Once BF_CUT goes

low, signifying S0 mode, the VDDQ supply recovers and

takes control of the VDDQ bus.

The memory read-write cycles start after the Silver box

POWER_OK signal goes high. The Silver-Box supply

POWER_OK signal goes high when all the voltages are

within a tight tolerance of the nominal voltage (typically

with 1-2%). Thus, the transition from S3 to S0 does not

cause a drop out in VDDQ voltage, since the higher VDDQ

currents follow the transition of POWER_OK signal from

the input Silver Box supply. The External VDDQ MOSFET,

which is capable of supplying the higher current, is

activated from the UVLO transition of the Input Rails,

which occur much earlier. Thus the External MOSFET will

be activated in time for the Memory’s Active state.

Initial Conditions

When the S5 and S3 go high (BF_CUT goes low) for the

first time, the VDDQ is supplied via the external MOSFET,

thus removing the burden of charging the output

capacitors via the internal linear VDDQ regulator.

Reset/restart

The SS/EN pin must be pulled low and high again to restart

the SC2615. This can be achieved by cycling the input

supplies, 3.3VCC/12VCC. There is a 50mV Hysteresis

on the UVLO threshold. When the rails are near the UVLO

thresholds, it is possible for noise to trigger the UVLO.

Since the reference for the UVLO threshold is derived

from the 5VSBY voltage, sufficient bypassing of the

5VSBY

improves noise immunity of the UVLO circuit.

The Short Circuit Protection function is disabled when

any of the input rails are below their respective UVLO

thresholds.

Back-feeding the Input Supply

When in S3 state, VDDQ is supplied by the internal linear

regulator. Current can flow back from the VDDQ supply

through the body diode of the Top MOSFET to the 3.3V

input supply from the Silver Box, which is off during this

state. This in turn shorts out the VDDQ bus and is not

Applications Information