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© 2004 Semtech Corp.

www.semtech.com

SC4510

POWER MANAGEMENT

INTRODUCTION

The SC4510 is designed to control and drive N-Channel

MOSFET synchronous rectified buck convertors. It has

additional features such as reference tracking, buffered

REFOUT that make it particularly attractive for tracking

output applications such as DDR memories. It can operate

the convertor in both the source and sink modes. The

switching frequency is programmable to optimize design.

The current mode switching regulator section features

Semtech’s patented Combi Sense technique for lossless

current sensing and provides a hiccup mode overcurrent

protection.

POWERING THE CONTROLLER

Supplies VIN, PVCC and AVCC from the input source are

used to power the SC4510. The AVCC and PVCC can be

tied to VIN supply or can be from separate source to

optimise efficiency. The AVCC supply provides the bias for

the oscillator, PWM switcher, voltage feedback, current

sense and the Power OK circuitry. PVCC is used to drive

the low and high side MOSFET gates. Minimum operating

limit for VIN is 2.5V typical. However, PVCC and AVCC have

higher UVLO limits as explained below. Maximum range

for all of the input and supply voltages is 16V.

STARTUP AND ENABLE

Startup is inhibited until AVCC input reaches its UVLO

threshold . The UVLO limit is 4.5V typical. When AVCC is

below the UVLO threshold, the soft start pin is pulled low

and output drivers are turned off. The power up sequence

is initiated by a 2 uA current source charging the soft start

capacitor connected to the SS pin. When the SS pin reaches

0.5V, the convertor will start switching. The reference input

of the error amplifier is ramped up with the soft-start signal.

The soft start duration is controlled by the value of the SS

cap. The soft start pin also functions as an enabler with

TTL compatible input thresholds. If the SS/EN pin is pulled

below 0.6V, the SC4510 is disabled and draws very low

current.

REFERENCE INPUT AND BUFFERED OUTPUT

The SC4510 comes with a low level built in reference of

0.5V. The non inverting input of the error amplifier is

brought out to provide additional flexibility and output

tracking functions. In the basic operation, the REF and

REFIN pins may be shorted together and the output voltage

feedback is provided at IN

In tracking applications such as DDR memories an external

reference may be brought in and applied at REFIN pin. The

range of applicable external voltage is up to 3V. The UV

and OV sensing thresholds for PGOOD output are centered

+12% around REFIN voltage.

The voltage at REFIN pin is buffered and put out as REFOUT.

This output tracks REFIN accurately within + 10 mV offset

or 0.5% of REFIN, whichever is higher. It can also source

up to 5 mA current. The REFOUT output is particularly useful

in DDR memory termination applications.

OSCILLATOR

The switching frequency F

external resistor using the following formula:

R

R

oscillator frequency is from 100 kHz to 1 MHz. The

maximum duty cycle available at any given frequency is

limited by minimum pulse width requirement which is

typically 250 nS. This gives a typical Dmax of 70% at the

highest frequency of 1 MHz or about 90% at 300 kHz.

The oscillator can be synchronised to an external clock that

is nominally faster than the internal frequency set by R

OSC.

The synchronising signal should be TTL compatible, with

transitions above 2.0V and below 0.6V. The external voltage

level applied should be lower than AVCC of the device.

GATE DRIVERS

The low side gate driver is supplied from PVCC and provides

a peak source/sink current of 1A. The high side gate drive

is capable of sourcing and sinking peak currents of 0.75A.

Protection logic provides a typical dead time of 90 nS to

ensure both the upper and lower MOSFETs will not turn on

simultaneously and cause a shoot through condition.

The high side Mosfet gate drive can be derived from the

PVCC supply using the classical bootstrap technique as

illustrated in the applications circuits. A bootstrap capacitor

is connected from BST to the Phase node while PVCC is

connected through a low V

to the BST. This will provide a gate to source voltage

approximately equal to the (VCC - Vfwd).

Functional Description