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© 2004 Semtech Corp.

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SC4510

POWER MANAGEMENT

Application Information (Contd.)

PCB LAYOUT FOR SC4510

Careful attention to layout requirements is necessary for

successful implementation of the SC4510 PWM controller.

High switching currents with fast rise and fall times are

present in the application and their effect on ground plane

voltage differentials must be understood and minimized.

A good layout with minimum parasitic loop areas will

a) reduce EMI

b) lower ground injection currents, resulting in electrically

“cleaner” grounds for the rest of the system and

c) minimize source ringing, resulting in more reliable gate

switching signals.

LAYOUT GUIDELINES

In the following Q

side MOSFETs respectively.

1) A ground plane should be used. The number and position

of ground plane interruptions should be minimised so as

not to compromise ground plane integrity. Isolated or semi-

isolated areas of the ground plane may be deliberately

introduced to constrain ground currents into particular

paths, such as the output capacitor or the Q

2) The high power, high current parts of the circuit should

be laid out first. The on time loop formed by the input

capacitor Cin, the high side FET Q

the output capacitor bank Cout must be kept as small as

possible. Another loop area to minimise is formed by low

side FET Q

bank Cout during the off period. These loops contain all

the high current, fast transition switching. Connections

should be as wide and as short as possible to minimize

loop inductance.

3) The connection between the junction of Q

output inductor should be a wide trace or copper region. It

should be as short as practical. Since this connection has

fast voltage transitions, keeping this connection short will

minimize EMI. Also keep the Phase connection to the IC

short. The top FET gate charge currents flow in this trace.

4) The output capacitor Cout should be located as close to

the load terminals as possible. Fast transient load currents

are supplied by Cout and connections between Cout and

the load must be kept short with wide copper areas to

minimize inductance and resistance. This will improve the

transient response to step loads.

5) The SC4510 is best placed over a quiet ground plane

area. Avoid pulse currents of the Cin, Q

this area. This analog ground plane should be connected

to the power ground plane at a “quiet” point near the input

capacitor. Under no circumstance should it be returned to

a point inside the Cin, Q

6) The SC4510 AGND pin is connected to the separate

analog ground plane with minimum lead length . All analog

grounding paths including decoupling capacitors, feedback

resistors, compensation components, soft start capacitor,

frequency and current-limit setting resistors should be

connected to the same plane.

7) Locate the critical filtering capacitors as close as possible

to their respective device. This is particularly true for the

current feedback filtering capacitor connected between

CS+ and CS-. A high value ceramic capacitor is also

recommended between PVCC and PGND pins close to the

device.