SC4612STRT datasheet(10/24 Pages) SEMTECH

10 / 24 page

 2007 Semtech Corp.

www.semtech.com

SC4612

POWER MANAGEMENT

Applications Information (Cont.)

The reference input of the error amplifier is effectively

ramped up with the soft-start signal. The error amp output

will vary between 100mV and 1.2V, depending on the duty

cycle. The error amp will be off until SS/EN reaches 0.7V

(TYP) and will move the output up to its desired voltage by

the time SS/EN reaches 1.3V. The gate drivers will be in

asynchronous mode until the FB pin reaches 500mV.

The intention for the asynchronous start up is to keep the

low side MOSFET from being switched on which forces the

low side MOSFETs body diode or the parallel Schottky di-

ode to conduct. The conduction by the diode prevents any

dips in an existing output voltage that might be present,

allowing for a glitch free start up in applications that are

sensitive to any bus disturbances.

During the asynchronous start up SC4612 monitors the

output and if within 10 cycles the FB has not reached the

internal soft start ramp level, the device switches to syn-

chronous mode. This provides an added protection in case

of short circuit at the output during the asynchronous start

when the bottom MOSFET is not being switched to provide

the R

DS-ON sensing current limit protection.

In case of a current limit, the gate drives will be held off

until the soft-start is initiated. The soft-start cycle defined

by the SS cap being charged from 800mV to 1.3V and

slowly discharged to achieve an approximate hiccup duty

cycle of 1% to minimize excessive power dissipation.

The part will try to restart on the next softstart cycle. If the

fault has cleared, the outputs will start . If the fault still

remains, the part will repeat the soft-start cycle above in-

definitely until the fault has been removed.

The soft-start time is determined by the value of the

softstart capacitor (see formula below).

≈

Oscillator Frequency Selection

The internal oscillator sawtooth signal is generated by

charging an external capacitor with a current source of

100µA charge current.

See Table 1 “Frequency vs. C

OSC” on page 14 to determine

oscillator frequency.

OVERCURRENT PROTECTION

SC4612 features low side MOSFET on-state Rds current

sensing and hiccup mode over current protection. ILIM pin

would be connected to DRV or PHASE via programming

resistors to adjust the over current trip point to meet

different customer requirements.

The sampling of the current thru the bottom FET is set at

~150ns after the bottom FET drive comes ON. It is done to

prevent a false tripping of the current limit circuit due to

the ringing at the phase node when the top FET is turned

OFF.

Internally overcurrent threshold is set to 100mV_typ. If

voltage magnitude at the phase node during sampling is

such that the current comparator meets this condition then

the OCP occurs.

Connecting a resistor from external voltage source such

as VDD, DRV, etc. to ILIM increases the current limit.

Connecting a resistor from ILIM to PHASE lowers the current

limit (see the block diagram in page 9).

Internal current source at ILIM node is ~20µA. External

programming resistors add to or subtract from that source

and hence vary the threshold.

The tolerance of the collective current sink at ILIM node is

fairly loose when combined with variations of the FET’s

Rds(on). Therefore when setting current limit some iteration

might be required to get to the wanted trip point.

Nonetheless, this circuit does serve the purpose of a hard

fault protection of the power switches. When choosing the

current limit one should consider the cumulative effect of

the load and inductor ripple current. As a rule of thumb,

the limit should be set at least x10 greater then the pk-pk

ripple current. Whenever a high current peak is detected,

SC4612 would first block the driving of the high side and

low side MOSFET, and then discharge the soft-start

capacitor. Discharge rate of the SS capacitor is 1/25 of

the charge rate.

Under Voltage Lock Out

Under Voltage Lock Out (UVLO) circuitry senses the VDD

through a voltage divider. If this signal falls below 4.5V (typi-

cal) with a 400mV hysteresis (typical), the output drivers

are disabled . During the thermal shutdown, the output

drivers are disabled.

SC4612STRT Datasheet(PDF) 10 Page - Semtech Corporation

SC4612STRT Datasheet(HTML) 10 Page - Semtech Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Download

Link URL