Application Circuits

The recommended circuit configuration for the 3-channel CDS mode operation is shown in the figure below (ADI mode

data output format). The recommended input coupling capacitor value is 0.1

mF.

A single ground plane is recommended for the HT82V24. A separate power supply may be used for DRVDD, the digital

driver supply, but this supply pin should still be decoupled to the same ground plane as with the rest of the HT82V24.

The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using exter-

nal digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of the

CDSCLK2 should occur in coincidence with or before the rising edge of ADCCLK. All 0.1

mF decoupling capacitors

should be located as close as possible to the HT82V24 pins. When operating in a single channel mode, the unused an-

alog inputs should be grounded.

Note:

For the 3-channel SHA mode, all of the above considerations also apply for this configuration, except that the

analog input signals are directly connected to the HT82V24 without the use of coupling capacitors. The OFF-

SET pin should be grounded if the inputs to the HT82V24 are to be referenced to ground, or a DC offset voltage

should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs.

The analog input signals must already be dc-biased between 0V and 2V, if OFFSET is connected to ground.

HT82V24

Rev. 1.00

13

September 7, 2005

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

A V D D

A V S S

V I N R

O F F S E T

V I N G

C M L

V I N B

R E F T

R E F B

A V S S

A V D D

S L O A D

S C L K

S D A T A

C D S C L K 1 / V S M P

C D S C L K 2

A D C C L K

O E

D V D D

D V S S

D 7 ( M S B )

D 6

D 5

D 4

D 3

D 2

D 1

D 0 ( L S B )

H T 8 2 V 2 4 ( C D S M o d e )

0 . 1 m F

1 . 0 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

1 0 m F

5 V / 3 V

R e d I n p u t

0 . 1 m F

5 V

C l o c k

I n p u t s

D a t a

O u t p u t s

S e r i a l

I n p u t s

0 . 1 m F

0 . 1 m F

G r e e n I n p u t

B l u e I n p u t

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1

2

3

4

5

6

7

8

9

1 0

V I N R

O F F S E T

C M L

R E F T

R E F B

A V S S

A V D D

S L O A D

S C L K

S D A T A

A V S S

A V D D

V S M P

A D C C L K

D V D D

D V S S

D 7

D 6

D 5

D 4

H T 8 2 V 2 4 ( C D S M o d e )

0 . 1 m F

1 . 0 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

1 0 m F

5 V / 3 V

R e d I n p u t

0 . 1 m F

5 V

C l o c k

I n p u t s

D a t a

O u t p u t s

S e r i a l

I n p u t s

0 . 1 m F

0 . 1 m F

0 . 1 m F

2 8

2 7

2 6

2 5

2 4

2 3

2 2

2 1

2 0

1 9

1 8

1 7

1 6

1 5

1

2

3

4

5

6

7

8

9

1 0

1 1

1 2

1 3

1 4

A V D D

A V S S

V I N R

O F F S E T

V I N G

C M L

V I N B

R E F T

R E F B

A V S S

A V D D

S L O A D

S C L K

S D A T A

C D S C L K 1 / V S M P

C D S C L K 2

A D C C L K

O E

D V D D

D V S S

D 7 ( M S B )

D 6

D 5

D 4

D 3

D 2

D 1

D 0 ( L S B )

H T 8 2 V 2 4 ( S H A M o d e )

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

1 0 m F

5 V / 3 V

R e d I n p u t

5 V

C l o c k

I n p u t s

D a t a

O u t p u t s

S e r i a l

I n p u t s

G r e e n I n p u t

B l u e I n p u t

D C L e v e l

2 0

1 9

1 8

1 7

1 6

1 5

1 4

1 3

1 2

1 1

1

2

3

4

5

6

7

8

9

1 0

V I N R

O F F S E T

C M L

R E F T

R E F B

A V S S

A V D D

S L O A D

S C L K

S D A T A

A V S S

A V D D

V S M P

A D C C L K

D V D D

D V S S

D 7

D 6

D 5

D 4

H T 8 2 V 2 4 ( S H A M o d e )

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

0 . 1 m F

1 0 m F

5 V / 3 V

R e d I n p u t

5 V

C l o c k

I n p u t s

D a t a

O u t p u t s

S e r i a l

I n p u t s

0 . 1 m F

D C L e v e l