SC2620SETRT datasheet(17/26 Pages) SEMTECH

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 2006 Semtech Corp.

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SC2620

POWER MANAGEMENT

Applications Information

ground, then the COMP voltage will continue to rise to its

2.4V upper limit. The SC2620 will reach its cycle-by-cycle

current limit sometime during the soft-start charging phase

(see Figure 17(c)). As described previously, the switches in

the SC2620 either do not turn on at all or for at least

105ns. With the output shorted, the error amplifier will

command the regulator to operate at full duty cycle. The

current limit comparator will turn off the switch if the switch

current exceeds 3.2A. However, this happens only after

the switch is turned on for 105ns. During switch off time,

the inductor current ramps down at a slow rate determined

by the forward voltage of the freewheeling diode and the

resistance of the short. If the resulting reverse volt-second

is insufficient to reset the inductor before the start of the

next cycle, then the inductor current will keep increasing

until the diode forward voltage becomes high enough to

achieve volt-second balance. This makes the current limit

comparator ineffective. Short circuit robustness will be

enhanced if the switching frequency is set below 500kHz

at high V

IN (> 20V). This increases the off time and keeps

the inductor current within bounds. The regulator is to be

checked under realistic short circuit condition as the

residual resistance of the short can significantly influence

circuit behavior. Shortening the soft-start interval from the

onset of switching to hiccup enable also makes short circuit

operation more robust. A 22-47nF soft-start capacitor is

found adequate for most applications.

In Figure 17(c), Channel 2 undergoes repeated shutdown

and restart (“hiccup”) with its output shorted. V

SS appears

as an asymmetrical triangular wave. The resistance of the

short appears to be 17m

Ω.

Power Good Indicator

The PGOOD1 pin (Pin 15) is the open-collector output of

Channel 1 power good comparator. This slow comparator

is incorporated with a small amount of hysteresis. The FB

low-to-high trip voltage of the power good comparator is

90% of the final regulation voltage. A pull-up resistor from

the PGOOD1 pin to the input supply or the regulator output

sets the logic high level of the comparator.

The power good comparator output becomes valid provided

that V

IN is above 0.9V. In shutdown the power good output

is actively pulled low. A power good pull-up resistor tied to

the input will therefore increase current drain during

shutdown. Tying the power good pull-up resistor to the

regulator output is preferred, as this will minimize the

shutdown supply current. In shutdown there is no voltage

at the switching regulator output or current in the PGOOD1

pull-up resistor. If the PGOOD1 output high level (= V

OUT) is

unacceptably low, then power good pull-up from the input

or a separate power supply will be the only choice.

Sequencing the Outputs

As mentioned above, pulling either soft-start pin low with

an external transistor shuts off the corresponding regulator

(Figure 10). Releasing the soft-start pin enables that

channel and allows it to start. Delaying the release of the

soft-start pin of one channel with respect to the other is a

straightforward way of sequencing the outputs. Figure

10(a) shows this method using two external transistors

1 and M2. M1 is turned off first, allowing channel 1 to

start. Channel 2 is then enabled after time T

PGOOD1 can also be used in conjunction with Channel 2

soft-start to delay start of that regulator. This method is

depicted in Figure 10(b). SS2 is pulled low and channel 2

is kept off until channel 1 output rises to 90% of its set

voltage.

Loop Compensation

Figure 11 shows a simplified equivalent circuit of a step-

down converter. The power stage, which consists of the

current-mode PWM comparator, the power switch, the

freewheeling diode and the inductor, feeds the output

network. The power stage can be modeled as a voltage-

controlled current source, producing an output current

proportional to its controlling input V

COMP.

Its

transconductance G

MP is 8Ω

-1

. With the current loop closed,

the control-to-output transfer function

COMP

OUT

has a

dominant-pole p

2 located at a frequency slightly higher

than that of the output filter pole.

OUT

−

≈

(8)

where C

1 is the output capacitor, ROUT is the equivalent

load resistance and n (depending on duty ratio, slope

compensation, frequency and passive components) is

usually between 1 and 2.

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