SC416 datasheet(10/34 Pages) SEMTECH

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SC416

one of the following occurs:

The FB comparator input drops to the

750mV reference, as sensed through the

FB pin or the VOUT pin

The Zero Cross detector trips, if psave is

active

The Negative Current Limit detector trips

If DL drives low because FB has dropped to 750mV, then

another DH on-time is started. This is normal operation

at heavy load (fully synchronous operation with either

DH or DL high except during transitions).

The Zero Cross detector monitors the voltage across the

low-side MOSFET during the DL high time and detects

when it reaches zero. If DL drives low because of the

Zero Cross detector, and psave is active, then both DH

and DL will remain low until FB drops to 750mV, at which

point the next DH on-time will begin. If a Zero Cross is

detected on eight consecutive cycles, then for each sub-

sequent switching cycle DL will shut off when the Zero

Cross detector trips; see the Psave Operation section.

When this occurs, both DH and DL will stay low until FB

drops to 750mV, which will begin the next DH on-time.

This is normal operation at light load, see the Psave Op-

eration section.

The Negative Current Limit detector trips when the drain

voltage at the low-side MOSFET reaches +80mV, indicat-

ing that a large negative current flows through the induc-

tor from VOUT. When this occurs, DL drives low. Both DH

and DL will then stay low until FB drops to 750mV, which

will begin the next DH on-time. Tripping Negative Cur-

rent Limit is rare.

To help reduce noise interaction between sides, the ris-

ing edge of each DH driver is inhibited momentarily if the

other side is switching. For example, if side1 is perform-

ing a DH or DL transition (up or down), then side2’s DH

driver is held off for roughly 30nsec to allow side1 to finish

switching.

Applications Information (continued)

VOUT Voltage Selection

Output voltage is regulated by comparing VOUT as seen

through a resistor divider to the internal 750mV refer-

ence, see Figure 2. Each output can be adjusted to a volt-

age between 0.75 – 5.25V. The output voltage is set by

the equation:

OUT

= 0.75 • (1 + R1/R2)

VOUT

To FB pin

Figure 2

Note: the parallel resistance of R1 and R2 should not be less than 2kΩ.

Using a smaller resistance can cause the IC to default to the internal

preset output voltages shown below.

There are fixed output voltages accessible through each

FB pin. If the FB pin is connected to either RTN or +5V,

then the IC will ignore the FB pin and instead regulate

the output voltage using the VOUT pin which is connect-

ed to internal resistors. The voltage selections available

are as shown:

FB Internal Voltage Selection

FBx = RTN

FBx = +5V

Side1

1.5V

1.8V

Side2

1.05V

1.25V

Note that each FB input operates independently.

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