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GL9711 Datasheet(PDF) 39 Page - GENESYS LOGIC

Part # GL9711
Description  PCI ExpressTM PIPE x1 PHY
PDF  42 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9711 Datasheet(HTML) 39 Page - GENESYS LOGIC

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GL9711 PCI Express
TM PIPE x1 PHY
©2000-2006 Genesys Logic Inc. - All rights reserved.
Page 39
Figure 8.2 – Definition of Output Timing
Table 8.1 – Input Setup, Hold Time and Output Timing for 8-bit SDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
3.99
4
4.01
ns
Duty-H
Duty cycle for PCLK high
35
-
50
%
TIS
Input setup time
-
-
1
ns
TIH
Input hold time
1
-
-
ns
TCO
Clock to output delay
-
2.7
3.2
ns
TOH
Output hold time
1
2.1
-
ns
Table 8.2 – Input Setup, Hold Time and Output Timing for 8-bit DDR Mode
Symbol
Parameter
Min
Typ
Max
Unit
TCYCLE
PCLK cycle time
7.98
8
8.02
ns
TIS
Input setup time
-
-
1.4
ns
TIH
Input hold time
0.5
-
-
ns
TCO
Clock to output delay
-
1.5
1.6
ns
TOH
Output hold time
0.8
1
-
ns



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