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HYS72T512341HKP Datasheet(PDF) 11 Page - Qimonda AG |
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HYS72T512341HKP Datasheet(HTML) 11 Page - Qimonda AG |
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11 / 32 page ![]() Internet Data Sheet Rev. 1.0, 2006-12 11 11032006-VX0M-M6IH HYS72T512341H[H/J/K]P-[3.7/5]-B Registered DDR2 SDRAM Modules TABLE 6 Abbreviations for Buffer Type TABLE 7 Abbreviations for Pin Type Abbreviation Description SSTL Serial Stub Terminated Logic (SSTL_18) CMOS CMOS Levels OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR. Abbreviation Description I Standard input-only pin. Digital levels. O Output. Digital levels. I/O I/O is a bidirectional input/output signal. AI Input. Analog levels. PWR Power GND Ground NU Not Usable NC Not Connected |
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