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RT9243GS Datasheet(PDF) 13 Page - Richtek Technology Corporation |
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RT9243GS Datasheet(HTML) 13 Page - Richtek Technology Corporation |
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13 / 18 page  RT9243 13 DS9243-07 March 2007 www.richtek.com DAC Offset Voltage & Droop Tuning The DAC output voltage decreases by VADJ to form the VCORE load droop (see Figure 3). Protection and SS Function The sensing circuit gets by local feedback. RSP = RSN to cancel the voltage drop caused by GM amplifier input bias current. IX is sampled and held just before low side MOSFET turns off (See Figure 2). Therefore, SP S L X R R I I × = Figure 2. Inductor Current and PWM Signal PWM Signal & High Side MOSFET Gate Signal Low Side MOSFET Gate Signal Inductor Current Falling Slope = Vo/L I L I L(AVG) I L(S/H) The DAC offset voltage is set by compensation network & VOSS pin external resistors by . The S/H current signals from power channels are injected to ADJ pin to create droop voltage. ∑ × = X ADJ ADJ I 2 R V 4 R R V 1 1 f VOSS × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ For OVP, the RT9243 detects the VCORE by VDIF pin voltage of the differential amplifier output. Eliminate the delay due to compensation network (compared to sensing FB voltage) for fast and accurate detection. The trip point of OVP is 140% of normal output level. The PWM outputs are pulled low to turn on the low side MOSFET and turn off the high side MOSFET of the synchronous rectifier at OVP. The OVP latch can only be reset by VCC or DVD restart power on reset sequence. The PGOOD detection trip point of VCORE is 92% lower than the normal level. The PGOOD open drain output pulls low when VCORE is lower than the trip point. For VID jumping issue, only power fail conditions (VCC & DVD are lower than trip point or OVP) reset the output low. Soft-start circuit generates a ramp voltage by charging external capacitor with 13 μA current after IC POR acts. The PWM pulse width and VCORE are clamped by the rising ramp to reduce the inrush current and protect the power devices. Over-current protection trip point is internally set at around 100 μA for each channel. OCP is triggered if one channel S/H current signal IX > Controller forces PWM output latched at high impedance to turn off both high and low side MOSFETs in the power stage and initial the hiccup mode protection. The SS pin voltage is pulled low with a 13 μA current after it is less than 90% VCC. The converter restarts after SS pin voltage < 0.2V. Three times of OCP disable the converter and only release the latch by POR acts (see Figure 4). . 5 . 1 9K V 6 . 0 × ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ Figure 3. DAC Offset Voltage & Droop Tune Circuit Current Source ∑ + - VOSS VOSS R V 1 I = 2I X1 2I X3 2I X2 FB ADJ V OSS R VOSS R F1 R ADJ V CORE EA V DAC V ADJ VOSS I 4 1 COMP 2I X4 > Figure 4. 0A 0V T0,T1 T2 T3,T4 TIME COUNT = 1 COUNT = 2 COUNT = 3 TIME Count = 1 Count = 2 Count = 3 S.S V CORE Overload Applied I LOAD SP S IN OUT IN OUT L(AVG) X(S/H) IN OUT IN OFF OFF OUT L(AVG) L(S/H) SP S L(S/H) X(S/H) R R 2L s 5 V V V V I I 200kHz fosc for s 5 V V V T , 2 T L V I I , R R I I × ⎥ ⎥ ⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎢ ⎢ ⎣ ⎡ × ⎥⎦ ⎤ ⎢⎣ ⎡ − − = = × ⎥ ⎦ ⎤ ⎢ ⎣ ⎡ − = × − = × = − μ μ |
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