RT9259CGS datasheet(11/15 Pages) RICHTEK

11 / 15 page

RT9259C

DS9259C-03

August 2007

www.richtek.com

ESR

OUT

ESR

The ESR zero is contributed by the ESR associated with

the output capacitance. Note that this requires that the

output capacitor should have enough ESR to satisfy stability

requirements. The ESR zero of the output capacitor

expressed as follows :

2) Compensation Frequency Equations

The compensation network consists of the error amplifier

and the impedance networks ZC and ZF as shown in

Figure 9.

Figure 9. Compensation Loop

fZ1

fP1

Figure 10 shows the DC-DC converter's gain vs. frequency.

The compensation gain uses external impedance networks

ZC and ZF to provide a stable, high bandwidth loop. High

crossover frequency is desirable for fast transient response,

REF

COMP

OUT

Figure 10. Bode Plot

Frequency

10Hz

100Hz

1.0KHz

10KHz

100KHz

1.0MHz

vdb(vo) vdb(comp2) vdb(lo)

-40

-60

100

10k

100k

-20

-40

-60

Loop Gain

Compensation

Gain

Modulator

Gain

Frequency (Hz)

but often jeopardize the system stability. In order to cancel

one of the LC filter poles, place the zero before the LC

filter resonant frequency. In the experience, place the zero

at 75% LC filter resonant frequency. Crossover frequency

should be higher than the ESR zero but less than 1/5 of

the switching frequency. The second pole is placed at half

the switching frequency.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature 125

°C. The

maximum power dissipation depends on the thermal

resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junction to ambient. The maximum power dissipation can

be calculated by following formula :

PD(MAX) = ( TJ(MAX)

− TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature 125

°C, TAis the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT9259C, where TJ(MAX) is the maximum junction

temperature of the die (125

°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance

θJA is layout dependent. For VQFN-16L 4x4

packages, the thermal resistance

θJA is 54°C/W on the

standard JEDEC 51-7 four-layers thermal test board.

The maximum power dissipation at TA = 25

°C can be

calculated by following formula :

PD(MAX) = ( 125

°C − 25°C ) / 54°C/W = 1.852 W for

QFN-16L 4x4 packages

PD(MAX) = ( 125

°C − 25°C) / 100°C/W = 1.000 W for

SOP-14 packages

PD(MAX) = ( 125

°C − 25°C ) / 110°C/W = 0.909 W for

SSOP-16 packages

The maximum power dissipation depends on operating

ambient temperature for fixed TJ (MAX) and thermal resistance

θJA. For RT9259C packages, the Figure 11 of derating

curves allows the designer to see the effect of rising

ambient temperature on the maximum power allowed.

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