RT9643 datasheet(13/17 Pages) RICHTEK

13 / 17 page

RT9643

DS9643-03 August 2007

www.richtek.com

To discharge the output capacitors, a 50

Ω load resistor is

switched in from VDDQ_IN to PGND whenever the IC is in

fault condition, or when EN is low. After a latched fault,

operation can be restored by recycling power or by toggling

the EN pin.

Under-Voltage Shutdown

If FB stays below the under-voltage threshold for 2

μs, the

“Fault latch” is set. This fault is prevented from setting

the fault latch during PWM soft-start (SS < 1.5V).

Over-Current Sensing

If the circuit’ s current limit signal (“ILIM det” as shown in

Figure 4) is high at the beginning of a clock cycle, a pulse

skipping circuit is activated and UGATE is inhibited. The

circuit continues to pulse skip in this manner for the next

8 clock cycles. If at any time from the 9th to the 16th

clock cycle, the “ILIM det” is again reached, the fault latch

is set. If “ILIM det” does not occur between cycle 9 and

16, normal operation is restored and the over-current circuit

resets itself. This fault is prevented from setting the fault

latch during soft-start (SS < 1.5V).

1. VDDQ_IN (PWM output voltage) > 1V and

2. FB < 100mV

Any of these 3 faults will set the fault latch. These 3 faults

can set the fault latch during the SS time (SS < 1.5V).

To ensure that FB pin open will not cause a destructive

condition, a 1

μA current source ensures that the FB pin

will be high if open. This will cause the regulator to keep

the output low, and eventually result in an Under-voltage

fault shutdown (after PWM SS complete).

Over-Temperature Protection

RT9643 incorporates an internal over temperature circuit

designed to protect the device during overload conditions.

If the junction temperature reaches a nominal temperature

of 150

°C, the over temperature circuit will shut the chip.

Normal operation is restored at when the die temperature

falls below 125

°C with internal Power On Reset asserted,

resulting in a full soft-start cycle. To accomplish this, the

over temperature comparator should discharge the SS

pin.

VTT Regulator

The VTT regulator is a simple and high-speed linear

regulator designed to generate termination voltage in

double data rate (DDR) memory system. The regulator is

capable of actively sinking or sourcing up to 1.25A while

regulating an output voltage to within 40mV. The output

termination voltage can be tightly regulated to track

1/2VDDQ_IN by two internal voltage divider resistors (50k

for each resistor) or two external voltage divider resistors

from the output of the PWM regulator.

The VTT regulator also incorporates a high-speed

differential amplifier to provide ultra-fast response in line/

load transient. Other features include extremely low initial

offset voltage, excellent load regulation, current limiting

in bi-directions.

The VTT regulator is enabled when S3#I is HIGH and the

PWM regulator's internal PGOOD signal is true. The VTT

regulator also includes its own PGOOD signal which is

high when VTT_SNS > 90% of REF_IN.

LDO Controller

The LDO controller combined with an external N-Channel

MOSFET pass element is used to provide 1.2V for the

Figure 6. Over Current Protection Waveform

Time (10

μs/Div)

UGATE (10V/Div)

IL (10A/Div)

LGATE (5V/Div)

PGOOD (5V/Div)

OVP / HS Fault / FB short to GND detection:

A HS Fault is detected when there is more than 0.5V

from PHASE to PGND 350ns after LGATE reaches 4V (same

time as the current sampling time).

OVP Fault Detection

occurs if FB > 115% VREF for 16

clock cycles. During soft-start, the output voltage could

potentially “run away” if either the FB pin is shorted to

GND or R1 is open. This fault will be detected if the following

condition persists for more than 14

μs during soft-start.

RT9643 Datasheet(PDF) 13 Page - Richtek Technology Corporation

RT9643 Datasheet(HTML) 13 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL